From: D. C. Sessions (firstname.lastname@example.org)
Date: Mon May 07 2001 - 07:44:08 PDT
On Monday 07 May 2001 04:15, RMELLISON@aol.com wrote:
# <BR>I have a few questions.
# <BR>What do the letters SLVS stand for? Is it the same as LV-CML? What is the
# <BR>driver and receiver structure? What are the rise/falltimes? Excluding
# <BR>copper interface problems, what is the expected upper bandwidth limit?
SLVS = Scalable Low-Voltage Signaling
Not, it's not LV-CML.
The driver _may_ be a simple NMOS totem-pole structure.
The receiver _may_ be a simple PMOS differential comparator.
Rise and fall times are application-specific.
Bandwidth, in our experience, has a lot more to do with the
limitations of CMOS than anything else. The bottlenecks have been
in the predriver and second-through-fourth receiver stages due to
the gain limitations imposed by speed requirements. That said, we're
seeing pretty decent behavior with cycle times down to 250 ps or so
in 0.18 micron processes.
-- | The race is not always to the swift, nor the battle to the strong. | | Because the slow, feeble old codgers like me cheat. | +--------------- D. C. Sessions <email@example.com> --------------+
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