From: Moran, Brian P (firstname.lastname@example.org)
Date: Thu May 03 2001 - 09:57:57 PDT
I wondered if this issue would ever surface again. I did alot of research on
this last year and never understood why the problem wasn't more universally
acknowledged. The only answer I could concieve of was that vendors were not
implmenting the PC133 DIMMs using the legacy topology rules.
The Intel Unbufferred DIMM spec was written for PC100 not PC133. It was
picked up and used as a topology reference in the consortium PC133
unbufferred DIMM spec, but I don't think the cosortium that wrote the PC133
spec ever looked at the clock closely at 133Mhz, or this issue would have
been obvious. Thats just my opinion, not Intel's
We were able to verify through frequency domain simulation that there is a
400Mhz (3rd harmonic) resonance on the DIMM clock network, further
exacerbated by the non-balanced clock tree topology. The tree happens to
have a total path length between the two SDRAMs, isolated on the other side
of the series resistor, of exactly the lamda/4 wavelength of 400Mhz. This
sets up a resonance which manifests itself as non-monotonic rising and
Its very easy to fix the problem on the DIMM by simply extending one branch
of the clock tree by 600mils, but of course thats not possible given the
number of DIMMS out there, and the fact that we don't own the spec anymore.
We found that placing a 22pf to 33pf capacitor at the driver corrected the
resonance problem, but you then get into issues with acheiving full voltage
swing and noise margins. The cap and series resistor was the solution we
ended up pursuing originally. We have since shifted to the cap at the
driver and an AC termination scheme, which provided better waveshape and
less flight time variance.
Brian P. Moran
Signal Integrity Engineer
From: Ting, Steve [mailto:Ting.Steve@inventec.com]
Sent: Thursday, May 03, 2001 1:54 AM
Subject: [SI-LIST] : PC133 Clock Quality [unbuffered DIMM]
Hi! SI list,
Brian P. Moran once asked this question last year, but seems no one
answered. So please allow me raise this question again.
According to all available information about PC133 unbuffered DIMM design on
the net, Intel's "PC SDRAM UNBUFFERED DIMM SPECIFICATION" seems to be the
only reference for traces topology. But my simulation results based on
Intel's clock topology for X8 configuration DIMM showed significant
oscillations on the clock rising/falling edges. My trace topology on MLB
from clock gen. to DIMM slot is point to point connection with one damping
resistor near clock gen. (typical topology on MLB). I believe that the
oscillations should be due to the unbalance clock tree defined in Intel's
spec, for I tried different clock gen. models, damping resistances and SDRAM
devices models and the oscillations still remain.
The only way I can do to avoid oscillations at clock receivers is to add
capacitor near damping resistor to slow down the slew rate to reduce the
reflection, if I assumed DIMM vendors would follow Intel's spec to route the
traces on DIMM. But I gain better SI at the expense of slower slew rate, and
I'm afraid the slow rising edge will violate slew rate spec (suppose 1V/nS).
As I checked the limited two DIMM module models we have, I found one DIMM
vendor followed Intel's spec but the other didn't to route their clock. Does
anyone noticed this problem and has any comments? Thanks!
With best regards,
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