From: Ting, Steve (Ting.Steve@inventec.com)
Date: Thu May 03 2001 - 01:53:56 PDT
Hi! SI list,
Brian P. Moran once asked this question last year, but seems no one
answered. So please allow me raise this question again.
According to all available information about PC133 unbuffered DIMM design on
the net, Intel's "PC SDRAM UNBUFFERED DIMM SPECIFICATION" seems to be the
only reference for traces topology. But my simulation results based on
Intel's clock topology for X8 configuration DIMM showed significant
oscillations on the clock rising/falling edges. My trace topology on MLB
from clock gen. to DIMM slot is point to point connection with one damping
resistor near clock gen. (typical topology on MLB). I believe that the
oscillations should be due to the unbalance clock tree defined in Intel's
spec, for I tried different clock gen. models, damping resistances and SDRAM
devices models and the oscillations still remain.
The only way I can do to avoid oscillations at clock receivers is to add
capacitor near damping resistor to slow down the slew rate to reduce the
reflection, if I assumed DIMM vendors would follow Intel's spec to route the
traces on DIMM. But I gain better SI at the expense of slower slew rate, and
I'm afraid the slow rising edge will violate slew rate spec (suppose 1V/nS).
As I checked the limited two DIMM module models we have, I found one DIMM
vendor followed Intel's spec but the other didn't to route their clock. Does
anyone noticed this problem and has any comments? Thanks!
With best regards,
**** To unsubscribe from si-list or si-list-digest: send e-mail to
firstname.lastname@example.org. In the BODY of message put: UNSUBSCRIBE
si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu
This archive was generated by hypermail 2b29 : Thu Jun 21 2001 - 10:11:49 PDT