Re: [SI-LIST] : troubleshoot differential clock

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From: Cosmin Iorga (iorgac@std.teradyne.com)
Date: Wed May 02 2001 - 13:18:47 PDT


Hi Perry,

can you describe in more details the termination scheme?

Cosmin

> Date: Wed, 02 May 2001 15:30:57 -0400
> From: "Perry Qu" <perry.qu@alcatel.com>
> X-Accept-Language: en
> MIME-Version: 1.0
> To: "si-list@silab.eng.sun.com" <si-list@silab.eng.sun.com>
> Subject: [SI-LIST] : troubleshoot differential clock
>
> Hi! Everyone:
>
> I have a case which need help from you guys:
>
> On one card, there is a LVPECL differential pair running from a buffer
> to the receiver. The total length of the pair is about 8 inches, with 50
> ohm termination at the receiver side. (2 resistors terminated to pwr/gnd
> for biasing also). The routing was not done properly, e.g., long
> parallel run with other differential pairs; unsymmetrical routing
> between the plus and minus, etc.
>
> In the lab, the signal measured at reciever side shows strong
> reflections, with non-monotonic points on the rising and falling edge,
> which is bad for clocks. The measurement is well repeatable and smells
> like some discontinueties problems. We did a simulation in XTK and we
> saw some reflections (not as bad). By adding a series termination at
> driver side (the driver is a really fast one, < 200 ps rise time), we
> manage to eliminate the reflections almost completely. However, we did
> not observe the same effect in the lab.
>
> The next thing we tried is to do some TDR measurement on the bare board.
> Since one of the TDR channel is not working properly, we can only
> measure the single-ended impedance. There is some dips here and there on
> both lines but none of them is bad enough to cause such bad signals at
> receiver side. We plan to do the the differential TDR once we have the
> sampling head repaired. But I doubt that is the reason.
>
> Really appreciate your comments/suggestions on this.
>
> Regards
>
> Perry Qu

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