RE: [SI-LIST] : RE: 2.5 GHz in FR4

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From: Larry Miller (ldmiller@rhapsodynetworks.com)
Date: Mon Apr 30 2001 - 11:15:38 PDT


Generally, more. Still playing with that, but most 3.125G SERDES's let you
program it, some on a per-channel basis. Our plug-in boards know what slot
they are in and who they are talking to, so we may put in hook for software
to set pre-emphasis based upon positions of the ends of the links (the
control traces are there, anyway!). Obviously, the more pre-emphasis you put
in the higher the EMI and crosstalk.
 
Larry Miller

-----Original Message-----
From: Mark Alexander [mailto:Mark.Alexander@xilinx.com]
Sent: Monday, April 30, 2001 10:37 AM
To: Larry Miller; si-list@silab.eng.sun.com
Subject: Re: [SI-LIST] : RE: 2.5 GHz in FR4

Larry,

On your 3.125 link, what level of pre-emphasis are you using? 15%? More?
Less?

Thanks,
mark
  
  

Larry Miller wrote:

 In our case (a back plane) we had striplines throughout the thickness of
the board (multiple routing layers). The board is nearly 0.25" thick. We did
the unused pad removal, as suggested here by others, and we also followed
the AMP design rules for pad size and antipad (annulus) diameter. If you do
that, you get very even characteristics. Yes, there is a short capacitance
dip in a TDR, but it is so short as to correspond to a very high frequency
or shorter rise time-- higher than we would be interested in.We got the
pitch on counter boring from the back and also on using blind vias from some
PCB vendors. We decided to try it without, since the papers I have seen on
these topics seem to deal with miniscule effects unless you are up in the
10GHz zone, which we were not. I would not argue with anyone who said they
wanted to do these things.Since this thread started, I have had the
opportunity to look closely at the board and plug in test boards both with
an HP 8753 VNA and a TEK CSA8000 scope with TDR plug in. Yes, you can see
the bobbles in the VNA sweep caused by the pin vias. You can also see the
small (<10%) impedance discontinuities at the connectors. The impedance
effects caused by routing through the HS-3 pin fields in the AMP-recommended
manner were miniscule (<0.5%), which I was very happy with.Furthermore, we
have used some SERDES eval boards to actually send 3.125 GHz 8B/10B PRBS
(random data) signals through the backplane. All is well. Good eye opening
(pre-emphasis required!) on 20-24" paths through 2 connectors. Very little
added jitter, relative to the SERDES outputs, which are in turn comparable
to the oscillator jitter. Plenty good for our purposes.Larry Miller

-----Original Message-----
From: RMELLISON@aol.com [ mailto:RMELLISON@aol.com
<mailto:RMELLISON@aol.com> ]
Sent: Monday, April 30, 2001 3:56 AM
To: ldmiller@rhapsodynetworks.com; mnudelman@tellium.com;
si-list@silab.eng.sun.com
Subject: Re: [SI-LIST] : RE: 2.5 GHz in FR4
 
Larry,
After reading all of the replies to the 2.5GHz questiion, I can see the need

for using stripline to keep phaseshift constant on long runs. In trying to
make the stubs a part of the transmission line, wouldn't it be advisable to
utilise most of the via as part of the line by using the stripline located
on
the opposite side of a card from the IC?
Consider the 8 layer stackup shown here for clarification.

------- Sig and IC layer
------------- Plane
------- Sig
------------- Plane
------------- Plane
------- Sig 2.5 GHz stripline
------------- Plane
------ Sig

The stub resulting from the the unused portion of the via is reduced in
length. The trick would be to make the vias look like the transmission line

impedance.

Another thought--It seems like an imbedded microstrip line would possess
almost the same qualities of a stripline in terms of dielectric affecting
phaseshift. Can a card be made so that the vias would go only from the IC
layer to an imbedded microstrip layer directly below? This would get rid of

any stubs. What do you think?

Richard Ellison
972-569-8317

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