From: Mike Saunders (email@example.com)
Date: Fri Apr 27 2001 - 10:19:13 PDT
You could use a 3-resistor level shifting tree from VCC to VEE, tapping
into the top node on the input side and then tapping off the bottom node to
shift the voltage levels down before entering your lvpecl logic. This
shouldn't affect your edges too much as long as the middle resistor is
fairly low in value, and shouldn't affect Tprop. hardly at all. Another
alternative would be to AC couple the signals, then re-set the DC bias with
a voltage divider on the lvpecl side. Either of these solutions would add
three components per leg.
One potential gotcha with either of these solutions could be "floating"
inputs which are actually terminated to an intermediate voltage (as occurs
in SSTL-II DDR SDRAM). In that case, you'll need to ensure that your input
logic always determines the signal in a defined state (ie- when the term.
voltage, after level shifting, is at or near the VBB of your input logic).
At 08:53 AM 4/27/2001 -0500, you wrote:
>Anybody know of 5V PECL to 3.3V LVPECL Translators - single or dual
>translator. I know ON Semi - MC100LVEL92 and Micrel - SY100EL92 make one,
>but these are triple translators.
>16305 36th Ave. North
>Minneapolis, MN 55446-2698
>Phone: (763) 268-3633
>Fax: (763) 268-3301
>Main: (763) 268-3300
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