RE: [SI-LIST] : Clock Jitter

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From: Grigoras, Adrian C (adrian.c.grigoras@intel.com)
Date: Tue Apr 24 2001 - 16:32:42 PDT


The PLL -"onchip" jitter should be accounted in the Thold for the receiver.
Otherwise for the system clock you should have not included jitter in your
calculations.
Adrian
-----Original Message-----
From: Coleman, Dave [mailto:dave.coleman@intel.com]
Sent: Tuesday, April 24, 2001 4:10 PM
To: 'Todd Westerhoff'; Coleman, Dave; si-list@silab.eng.sun.com
Subject: RE: [SI-LIST] : Clock Jitter

Yes, since internal latching and signal generation may be from a tap of a
PLL, it too will add jitter, which we generally "eat" timing margin both in
the output as well as input timing equations. Just wanted to point out that
even without a PLL, there are other sources of "jitter" (which I identify as
random timing variations - different than skew) along the clock paths (and
data paths) that affect both the setup and hold time.

Dave

-----Original Message-----
From: Todd Westerhoff [mailto:twester@hhnetwk.com]
Sent: Tuesday, April 24, 2001 3:44 PM
To: Coleman, Dave; si-list@silab.eng.sun.com
Subject: RE: [SI-LIST] : Clock Jitter

Very Good Point! (Note the use of capitalization).

You're absolutely right, Dave - I was making the assumption that all devices
are directly referencing the same buffer's output, which doesn't have to be
the case.

As a matter of fact, when you have PLL's in the path between the master
reference clock and the driver/receivers - doesn't the PLL jitter (or some
part of it) actually work its way back into the equations?

As usual, the things that look simple - aren't.

Todd.

-----Original Message-----
From: owner-si-list@silab.eng.sun.com
[mailto:owner-si-list@silab.eng.sun.com]On Behalf Of Coleman, Dave
Sent: Tuesday, April 24, 2001 5:52 PM
To: 'si-list@silab.eng.sun.com'
Subject: FW: [SI-LIST] : Clock Jitter

This is assuming, though, that the only clock jitter is from the clock
driver source. There can be other sources of clock jitter along the
different clock paths. For example, the traces can have random signal
coupling that can introduce "jitter" into the hold equation. Also, the
receiving component can have noise (many sources) that can introduce
threshold shifts pulling in or pushing out the latch time.

Dave

-----Original Message-----
From: Todd Westerhoff [mailto:twester@hhnetwk.com]
Sent: Tuesday, April 24, 2001 2:17 PM
To: dkhatri; si-list@silab.eng.sun.com
Subject: RE: [SI-LIST] : Clock Jitter

Clock jitter normally does not apply to hold equations because both the
driver and receiver are referencing the same clock edge.

Todd.

-----Original Message-----
From: owner-si-list@silab.eng.sun.com
[mailto:owner-si-list@silab.eng.sun.com]On Behalf Of dkhatri
Sent: Tuesday, April 24, 2001 3:45 PM
To: si-list@silab.eng.sun.com
Subject: [SI-LIST] : Clock Jitter
Importance: Low

Hi all,
I have a question regarding the Clock jitter term. whether we should be
using CLOCK JITTER term in the Hold Equations or not.Can any body please
explain me whether we should or should not use it and why?

Thanks,
Dirgha Khatri
Simulation Engineer
Micron Technology

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