FW: [SI-LIST] : Clock Jitter

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From: Coleman, Dave (dave.coleman@intel.com)
Date: Tue Apr 24 2001 - 14:52:27 PDT


This is assuming, though, that the only clock jitter is from the clock
driver source. There can be other sources of clock jitter along the
different clock paths. For example, the traces can have random signal
coupling that can introduce "jitter" into the hold equation. Also, the
receiving component can have noise (many sources) that can introduce
threshold shifts pulling in or pushing out the latch time.

Dave

-----Original Message-----
From: Todd Westerhoff [mailto:twester@hhnetwk.com]
Sent: Tuesday, April 24, 2001 2:17 PM
To: dkhatri; si-list@silab.eng.sun.com
Subject: RE: [SI-LIST] : Clock Jitter

Clock jitter normally does not apply to hold equations because both the
driver and receiver are referencing the same clock edge.

Todd.

-----Original Message-----
From: owner-si-list@silab.eng.sun.com
[mailto:owner-si-list@silab.eng.sun.com]On Behalf Of dkhatri
Sent: Tuesday, April 24, 2001 3:45 PM
To: si-list@silab.eng.sun.com
Subject: [SI-LIST] : Clock Jitter
Importance: Low

Hi all,
I have a question regarding the Clock jitter term. whether we should be
using CLOCK JITTER term in the Hold Equations or not.Can any body please
explain me whether we should or should not use it and why?

Thanks,
Dirgha Khatri
Simulation Engineer
Micron Technology

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