RE: [SI-LIST] : Clock Jitter

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From: Moran, Brian P (brian.p.moran@intel.com)
Date: Tue Apr 24 2001 - 14:25:47 PDT


Dirgha,

My last response assumes a common clock architecture. Also to clarify,
downstream jitter which is common and in phase with all clock branches can
still be thought of as common mode jitter and ignored for hold purposes.
Trying to figure out what is common mode and what is not can be difficult so
I usually treat all jitter after the source as dynamic skew.

Brian P. Moran
Signal Integrity Engineer
Intel Corporation
brian.p.moran@intel.com

-----Original Message-----
From: dkhatri [mailto:dkhatri@micron.com]
Sent: Tuesday, April 24, 2001 12:45 PM
To: si-list@silab.eng.sun.com
Subject: [SI-LIST] : Clock Jitter
Importance: Low

Hi all,
I have a question regarding the Clock jitter term. whether we should be
using CLOCK JITTER term in the Hold Equations or not.Can any body please
explain me whether we should or should not use it and why?

Thanks,
Dirgha Khatri
Simulation Engineer
Micron Technology

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