RE: [SI-LIST] : Clock Jitter

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From: Moran, Brian P (brian.p.moran@intel.com)
Date: Tue Apr 24 2001 - 14:15:19 PDT


Dirgha,

Clock jitter which is common to all branches of the clock tree, such as that
originating at a PLL source, does not get subtracted from hold margin
because hold is with respect to any single edge, not with respect to two
consequtive edges, such as setup margin. Basically this type of jitter can
be thought of as frequency jitter, and hold is not dependent on frequency.
On the other hand, jitter which is injected further down stream and is not
common to all clcok branches should be considered as dynamic skew and should
be subtrated from both hold and setup.

Brian P. Moran
Signal Integrity Engineer
Intel Corporation
brian.p.moran@intel.com

-----Original Message-----
From: dkhatri [mailto:dkhatri@micron.com]
Sent: Tuesday, April 24, 2001 12:45 PM
To: si-list@silab.eng.sun.com
Subject: [SI-LIST] : Clock Jitter
Importance: Low

Hi all,
I have a question regarding the Clock jitter term. whether we should be
using CLOCK JITTER term in the Hold Equations or not.Can any body please
explain me whether we should or should not use it and why?

Thanks,
Dirgha Khatri
Simulation Engineer
Micron Technology

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