From: Kai Keskinen (firstname.lastname@example.org)
Date: Fri Apr 20 2001 - 05:27:42 PDT
You can also use the .ic (initial conditions) statement of HSPICE to avoid
the long settling times for this kind of simulation.
Equipment and Network Interconnect
Nortel Dependability Solutions and Performance Networks (NSPaN)
> -----Original Message-----
> From: Degerstrom, Michael J. [SMTP:email@example.com]
> Sent: Tuesday, April 17, 2001 5:46 PM
> To: firstname.lastname@example.org; email@example.com
> Subject: RE: [SI-LIST] : 2.5ghz simulations
> You are AC coupling the output to the input. Make
> sure that the output is 'back-terminated', i.e., that
> is has 50 ohm resistors tied to the positive supply
> on the chip itself.
> Your CML is probably back-terminated. So here is another suggestion.
> Transient simulations are difficult with large AC coupling
> capacitors. You have to run the simulation for a long
> time for the proper biasing to be seen at the input. Once
> things have settled out then you can begin to analyze your
> results. I think the 'RC' time constant will be about
> 2*Zo*C where Zo is the impedance of your interconnect
> and C is your AC coupling capacitor. You probably want
> to run for 2 or 3 time constants depending on your application.
> By the way, I often setup DC biasing that switches off shortly
> after the transient simulation begins. This way I don't have
> to wait for transients to settle out.
> Mike Degerstrom Email: firstname.lastname@example.org
> Mayo Clinic; 200 1st Street SW ; Rochester, MN 55905
> Phone: (507) 538-5462 FAX: (507) 284-9171
> WWW: http://www.mayo.edu/sppdg/sppdg_home_page.html
> > -----Original Message-----
> > From: Sreejith Varma [mailto:email@example.com]
> > Sent: Tuesday, April 17, 2001 1:08 PM
> > To: firstname.lastname@example.org
> > Subject: [SI-LIST] : 2.5ghz simulations
> > HI All,
> > i am doing a differentail pair simulation using Cadence allegro
> > tool. as it is diff. pair i am doing the post route sim on the
> > allegro itself.
> > it is a 2.5ghz signal (a clock). it is a CML interface. when i do
> > the simulation, i see the differential signals, both input and output
> > DC shifted, quite apart.
> > the topology is something like this
> > tx +/- ---> ac_coupling capacitor (10 nF) ---> trans. line ---> rx +/-
> > the cml inputs are internally biased and terminated. when i run the
> > rise time sim. the tool reports that the receiver doesnt meet the
> > thresholds(2.2 v of vih and 1.76v of vil). what i see is a waveform
> > of 500 mv peak to peak biased around 3 v (+ sig) and 2 v (- sig).
> > another observation is that the rising waveform as per the IBIS model
> > is not observed at the output pin, this also dc shifted and
> > quite different
> > in rise time than in IBIS model..
> > any body have any idea what could be going wrong? or i am
> > doing something
> > grossly wrong !!!!!
> > thanks in advance..
> > sreejith
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