RE: [SI-LIST] : Power Supply decoupling for Video Accelerator

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From: Michael Nudelman (mnudelman@tellium.com)
Date: Fri Apr 20 2001 - 08:49:19 PDT


Massimo,

What you described:

>>>one very good ground plane and one high
capacitance capacitor at the entrance of the power supply into the board
and one well selected capacitor (parasitic inductance, charge, ...) close
to the chip pins.
>>>

may not be enough, at least the part with "one well selected capacitor
(parasitic inductance, charge, ...) close
to the chip pins". Of course, it depends on your application, but generally
you want well-decoupled chip and this may mean well-decoupled planes and the
VCC/GND pins run to their respective planes with short fat traces and vias.

However bunch of different grounds etc may be an overkill, or even a
detrimental practice. What happens sometimes (and I did see exactly that)
the application people in the chip manufacturing company create a small eval
board and connect it to the power supplies in such a way that the DUT
requires some crazy de-coupling techniques.

When you have something really sensitive (PLL loop VCC, for example) you may
want to filter the VCC by a simple PI, using an inductance and an additional
cap. In case of more sensitivity you need to use something drastic. But you
have to find out how sensitive your chip is.

Mike.

-----Original Message-----
From: Massimo Polignano [mailto:massimo.polignano@esaote.com]
Sent: Friday, April 20, 2001 08:47
To: si-list@silab.eng.sun.com
Subject: [SI-LIST] : Power Supply decoupling for Video Accelerator

Hallo everybody!

We are going to use a Video Accelerator (69000 Chips HiQVideo) to drive a
LCD. In the data book the manufacturer seems to be very much concerned with
PCB layout and power supply decoupling. They suggest the use of three
different grounds and power supply filtering using more than one LC or RC
cell and more than one decoupling capacitor of the same value in parallel.

Usually I prefer to have just one very good ground plane and one high
capacitance capacitor at the entrance of the power supply into the board
and one well selected capacitor (parasitic inductance, charge, ...) close
to the chip pins. Facing suggestions like those above, one is always in
doubt whether the chip designer made accurate tests, simulations and
prototyping or he just wants to stay on the safe side.

Does anybody out of there have any thought on the matter?

Thanks
m.p.
-------------------------------------------------------------
ESAOTE S.p.A. Massimo Polignano
Research & Product Development Design Quality Control Mngr
Via di Caciolle,15 tel:+39.055.4229402
I- 50127 Florence fax:+39.055.4223305
        e-mail: massimo.polignano@esaote.com

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