RE: [SI-LIST] : 2.5ghz simulations

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From: Degerstrom, Michael J. (degerstrom.michael@mayo.edu)
Date: Thu Apr 19 2001 - 10:27:02 PDT


Sreejith,

It has been a while since I did this. I don't use cadence
for simulations but in hspice I would probably use a switch
circuit to pull down the input by vswing/2 from its AC
biases value. This is assuming your
pulse train starts low and then goes high. Your switch
is initially closed but then opens shortly after the
transient simulation starts.

If this approach does not work then hopefully I've given
you some suggestions. If you didn't have a switch then
I guess you could push or pull current at the input node
to and experiment to get the correct vswing/2 offset. Then
shut the current source off as the incident voltage signal
arrives.

Mike

> -----Original Message-----
> From: Sreejith Varma [mailto:varma@blr.paxonet.com]
> Sent: Thursday, April 19, 2001 11:39 AM
> To: Degerstrom, Michael J.; si-list@silab.eng.sun.com
> Subject: RE: [SI-LIST] : 2.5ghz simulations
>
>
> HI Mike,
>
> >By the way, I often setup DC biasing that switches off shortly
> >after the transient simulation begins. This way I don't have
> >to wait for transients to settle out.
>
> how do i do this ? is this set in the sim. tool ? if yes then
> how do i do this in cadence?
>
> thanks in advance
> sreejith
>
>
> _______________________________________________________________
> Mike Degerstrom Email: degerstrom.michael@mayo.edu
> Mayo Clinic; 200 1st Street SW ; Rochester, MN 55905
> Phone: (507) 538-5462 FAX: (507) 284-9171
> WWW: http://www.mayo.edu/sppdg/sppdg_home_page.html
> _______________________________________________________________
>
>
> > -----Original Message-----
> > From: Sreejith Varma [mailto:varma@blr.paxonet.com]
> > Sent: Tuesday, April 17, 2001 1:08 PM
> > To: si-list@silab.eng.sun.com
> > Subject: [SI-LIST] : 2.5ghz simulations
> >
> >
> > HI All,
> >
> > i am doing a differentail pair simulation using Cadence allegro
> > tool. as it is diff. pair i am doing the post route sim on the
> > allegro itself.
> >
> > it is a 2.5ghz signal (a clock). it is a CML interface. when i do
> > the simulation, i see the differential signals, both input
> and output
> > DC shifted, quite apart.
> >
> > the topology is something like this
> >
> > tx +/- ---> ac_coupling capacitor (10 nF) ---> trans. line
> ---> rx +/-
> >
> > the cml inputs are internally biased and terminated. when i run the
> > rise time sim. the tool reports that the receiver doesnt meet the
> > thresholds(2.2 v of vih and 1.76v of vil). what i see is a waveform
> > of 500 mv peak to peak biased around 3 v (+ sig) and 2 v (- sig).
> >
> > another observation is that the rising waveform as per the
> IBIS model
> > is not observed at the output pin, this also dc shifted and
> > quite different
> > in rise time than in IBIS model..
> >
> > any body have any idea what could be going wrong? or i am
> > doing something
> > grossly wrong !!!!!
> >
> > thanks in advance..
> > sreejith
> >
> >
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