From: Sreejith Varma ([email protected])
Date: Thu Apr 19 2001 - 09:38:58 PDT
>By the way, I often setup DC biasing that switches off shortly
>after the transient simulation begins. This way I don't have
>to wait for transients to settle out.
how do i do this ? is this set in the sim. tool ? if yes then
how do i do this in cadence?
thanks in advance
Mike Degerstrom Email: [email protected]
Mayo Clinic; 200 1st Street SW ; Rochester, MN 55905
Phone: (507) 538-5462 FAX: (507) 284-9171
> -----Original Message-----
> From: Sreejith Varma [mailto:[email protected]]
> Sent: Tuesday, April 17, 2001 1:08 PM
> To: [email protected]
> Subject: [SI-LIST] : 2.5ghz simulations
> HI All,
> i am doing a differentail pair simulation using Cadence allegro
> tool. as it is diff. pair i am doing the post route sim on the
> allegro itself.
> it is a 2.5ghz signal (a clock). it is a CML interface. when i do
> the simulation, i see the differential signals, both input and output
> DC shifted, quite apart.
> the topology is something like this
> tx +/- ---> ac_coupling capacitor (10 nF) ---> trans. line ---> rx +/-
> the cml inputs are internally biased and terminated. when i run the
> rise time sim. the tool reports that the receiver doesnt meet the
> thresholds(2.2 v of vih and 1.76v of vil). what i see is a waveform
> of 500 mv peak to peak biased around 3 v (+ sig) and 2 v (- sig).
> another observation is that the rising waveform as per the IBIS model
> is not observed at the output pin, this also dc shifted and
> quite different
> in rise time than in IBIS model..
> any body have any idea what could be going wrong? or i am
> doing something
> grossly wrong !!!!!
> thanks in advance..
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