From: Ingraham, Andrew (Andrew.Ingraham@compaq.com)
Date: Tue Apr 17 2001 - 14:26:49 PDT
Capacitively coupled logic signals can be difficult to simulate in SPICE or
a SPICE-like tool. (I don't know whether this applies to the simulator you
The basic problem is the way SPICE does .TRANsient simulations. A transient
simulation assumes that everything is quiescent for all time before t=0,
then things suddenly start moving.
Therefore, your outputs weren't switching until t>0. Probably, one
differential output pin was high and the other was low. On the other side
of the coupling capacitors, the two pins self-bias to an equal (or similar)
DC bias voltage to one another. The result is unequal voltages across the
Then when the signal starts switching, it takes some time (perhaps a very
long time) for the bias point to re-establish itself correctly. Meanwhile,
the two signals on the other side of the coupling capacitors are biased
apart from one another. And it may also affect the signal at the output
driver itself (because the output currents aren't "normal" yet).
This is what really happens (in a real circuit) if you turned off the clocks
for a very long time and observed what happens when you first turn them on.
You may need to wait dozens or thousands of cycles for the final bias point
to be established.
There are at least three ways to deal with this in SPICE.
One is to wait a long time before looking at your signals. How long,
depends on the value of those capacitors.
Another is to force initial conditions in SPICE to get the "right" bias
point once the clocks start running. This may take some work to find the
right initial conditions, but it makes simulations much faster.
A third option, which you may or may not have, would be to start the
simulation with the output drivers forcing mid-value output voltages. Each
output pin is mid-way between high and low states.
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