RE: [SI-LIST] : Methods to introduce noise in power planes

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From: Kai Keskinen (keskinen@nortelnetworks.com)
Date: Tue Apr 17 2001 - 05:05:27 PDT


Ray and others:

We are using SPICE models of chips and injecting power supply noise to the
power inputs of the chip models to get a feel for the degradation we will
get on the real board. Does anyone have a recommendation for how to
determine the power spectrum of the noise? Similarly, for actual injection
of noise to the power plane, how do you determine what frequencies to
inject?

Thanks,

Kai Keskinen
Equipment and Network Interconnect
Nortel Dependability Solutions and Performance Networks (NSPaN)
keskinen@nortelnetworks.com

> -----Original Message-----
> From: Ray Anderson [SMTP:Raymond.Anderson@Sun.COM]
> Sent: Monday, April 16, 2001 3:34 PM
> To: si-list@silab.eng.sun.com
> Subject: Re: [SI-LIST] : Methods to introduce noise in power planes
>
>
> Although there are several ways of doing this, one method which we
> use in our lab and have had really good results with is to utilize
> a commercial broadband bias tee to inject the noise.
>
> Feed the DC power to your system through the tee's RF choke. Inject
> your desired noise into the system via the capacitively coupled port.
>
> We've also tried building up ferrite transformers etc. to try to
> match the 'noise' to the ultra low impedance of the boards power
> distribution system but found the bias tee method works much better.
>
> Ray Anderson
> Sun Microsystems Inc.
>
>
> >Hello All.
> >I have a test board, which has clock drivers and SERDES on it. I want to
> >observe the effect of power supply noise on the performance of SERDES
> >and the jitter on the clock driver output. For that, I would like to
> >introduce noise in the power planes. Can any body suggest how I could do
> >that?
> >
> >Thanks and regards
> >Sunil Kumar
>
>
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