RE: [SI-LIST] : Diff clocks length matching

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From: Dagostino, Tom (tom_dagostino@mentorg.com)
Date: Fri Apr 13 2001 - 16:23:05 PDT


Mary

I was responding to two items brought up in the discussion. I never
justified 2 mil matching.

>As Lee Ritchey would say, and I like to quote as often as possible "Show
>me the data."

and

>I'd be generally very happy to have differential skews matched to
>within 5% of the edge rate for most systems.

>10Gbps - about 10 mils
>3.2 Gbps - about 20 mils
>2 Gbps - about 25 mils
>1 Gbps - about 50 mils
>622 Mbps - about 100 mils

I was addressing Scott's statement for high frequencies he only needs 3 psec
matching for 10 Gbps to 30 psec for 622 Mps and Mitch's give me some real
data.

Without a context for these discussions there can be no discussion. I
showed an example from work in a company I used to work for how one cannot
just apply some kind of rule-of-thumb to dismiss a design constraint. I'd
hate to see people use Scott's numbers as a rule of thumb because I know
Scott, I know Scott hates rules of thumb. I was not trying to justify 2 mil
matching, just putting some real numbers from real applications on the
table.

In an application like this the 3 ADC's would have the same pins driven by
the clock so only the variation in the parasitics would cause a mismatch.
The imbalance's would be the same for all three clock nets hopefully so the
three nets would see the same delay as good as board processing can make
them.

Yes, nothing is perfect, but I was just showing how a simple 20 MHz clock
may have tighter timing constraints than outlined in Scott's examples.

 

Tom Dagostino
IBIS and Tau Modeling Manager
SDD
Mentor Graphics Corp.
503-685-1613
tom_dagostino@mentor.com

-----Original Message-----
From: Mary [mailto:mary@advocate.net]
Sent: Friday, April 13, 2001 3:19 PM
To: 'Signal Integrity'
Subject: RE: [SI-LIST] : Diff clocks length matching

This is an interesting mathematical exercise, but it's not a valid
justification
for controlling the lengths of PCB traces to within 2 mils. As pointed out
by Scott and others, the package parasitics and impedance imbalance
will swamp a 0.3 psec delay skew.
 
Mary

-----Original Message-----
From: owner-si-list@silab.eng.sun.com
[mailto:owner-si-list@silab.eng.sun.com]On Behalf Of Dagostino, Tom
Sent: Thursday, April 12, 2001 1:24 PM
To: 'Scott McMorrow'; cadpro2k@dacafe.com
Cc: Sainath Nimmagadda; Signal Integrity
Subject: RE: [SI-LIST] : Diff clocks length matching

There are very common applications where much tighter timing than you would
expect is required.
 For example digitizing video signals presents some interesting timing
constraints. Let's assume
there are the R, G and B signals getting to 3 10 Bit ADCs at the same time.
Each of these
converters will run at 20 MS/sec. Let's assume the worst case, a 10 MHz
sine wave input of 1 Volt
amplitude. We want to digitize all the components at the same time. In
this case the same time
will be defined as there will be no more than 1/2 bit in amplitude
difference between the three
signals due to time differences in sampling.
 
The math is straight forward.
 
signal = 1sin2Pi10^7
the slew rate is the derivative
 
2Pi10^^7cos2Pi10^7
 
evaluated at the max slope
 
2Pi10^7 V per sec
 
The amount of time it takes for this slew rate to travel 1/2 LSB of the ADC
is
 
1mV/2Pi10^7
 
or about 15.9 psec
 
Do the same exercise at 100 MHz input signal and you would get 1.59 psec.
That would be the
total budget for timing errors. Of that, how much do you want the board to
contribute?
 

Tom Dagostino
IBIS and Tau Modeling Manager
SDD
Mentor Graphics Corp.
503-685-1613
tom_dagostino@mentor.com

 

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