# RE: [SI-LIST] : Diff clocks length matching

From: Mary ([email protected])
Date: Fri Apr 13 2001 - 15:18:33 PDT

This is an interesting mathematical exercise, but it's not a valid
justification
for controlling the lengths of PCB traces to within 2 mils. As pointed out
by Scott and others, the package parasitics and impedance imbalance
will swamp a 0.3 psec delay skew.

Mary
-----Original Message-----
From: [email protected]
[mailto:[email protected]]On Behalf Of Dagostino, Tom
Sent: Thursday, April 12, 2001 1:24 PM
To: 'Scott McMorrow'; [email protected]
Subject: RE: [SI-LIST] : Diff clocks length matching

There are very common applications where much tighter timing than you
would expect is required.
For example digitizing video signals presents some interesting timing
constraints. Let's assume
there are the R, G and B signals getting to 3 10 Bit ADCs at the same
time. Each of these
converters will run at 20 MS/sec. Let's assume the worst case, a 10 MHz
sine wave input of 1 Volt
amplitude. We want to digitize all the components at the same time. In
this case the same time
will be defined as there will be no more than 1/2 bit in amplitude
difference between the three
signals due to time differences in sampling.

The math is straight forward.

signal = 1sin2Pi10^7
the slew rate is the derivative

2Pi10^^7cos2Pi10^7

evaluated at the max slope

2Pi10^7 V per sec

The amount of time it takes for this slew rate to travel 1/2 LSB of the

1mV/2Pi10^7

Do the same exercise at 100 MHz input signal and you would get 1.59 psec.
That would be the
total budget for timing errors. Of that, how much do you want the board
to contribute?

Tom Dagostino
IBIS and Tau Modeling Manager
SDD
Mentor Graphics Corp.
503-685-1613
[email protected]

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