From: Zabinski, Patrick J. ([email protected])
Date: Wed Apr 11 2001 - 04:15:35 PDT
We are using (older) commercial asynch SRAM that has some
form of address transition detection circuitry.
In brief, the SRAM monitors the address bus. If bus does not
transition states, the SRAM goes to a low power state. When
a bit on the bus transitions states, the SRAM thinks something
is about to happen and wakes up.
Can anyone point me to references on address transition detection
circuitry such as this? We believe it might be causing us problems,
and I'd like to read up on how it works and any sensitivities
it might have. Any references to
app notes, papers, text books, etc. will be appreciated.
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