From: Bradley S Henson ([email protected])
Date: Wed Apr 04 2001 - 09:49:57 PDT
In both my experience and reading, it is not generally considered good
practice to re-buffer a common, remote clock oscillator and distribute it
to multiple Fibre Channel SERDES. I have seen the results so bad that the
link would not even acquire because of the phase noise/jitter.
I am reviewing a design that uses many Vitesse 7212s. Their 100MHz clocks
are sourced from a remote master oscillator that is rebuffered and
distributed through 2 CMOS ASICs of modest technology (i.e., not the
fastest 0.18, or even 0.25 um stuff). The final clocks are source
terminated and sent to the 7212. I don't have, and can't get, phase noise
specs for the ASICs, but they are doing a lot of general purpose
processing, and the clock outputs are not specially isolated. I suspect a
good deal of jitter. I'm very concerned that the resulting links might be
unreliable, especially since we have not breadboarded it. The BER for the
link is likely several orders of magnitude greater than fibre channel, but
I'm even worried it may not meet that kind of rate. Like I said, I recently
witnessed a Vitesse 7216 breadboard that tried a common oscillator (against
my advice) and it would not even acquire.
I think Vitesse discourages this practice. Is there any reason I should not
raise hell? The design is getting painfully close to release. Has anyone
had a good experience with rebuffered clocks on Gbit SERDES?
Brad Henson, Raytheon
**** To unsubscribe from si-list or si-list-digest: send e-mail to
[email protected] In the BODY of message put: UNSUBSCRIBE
si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu
This archive was generated by hypermail 2b29 : Thu Jun 21 2001 - 10:11:26 PDT