**From:** ARiazi (*ARIAZI@prodigy.net*)

**Date:** Sat Mar 31 2001 - 11:37:26 PST

**Next message:**Ingraham, Andrew: "RE: [SI-LIST] : Nyquest Sampling Rate"**Previous message:**Daniel, Erik S.: "RE: [SI-LIST] : Nyquist Sampling Rate"**In reply to:**abe riazi: "[SI-LIST] : Diode Modeling"**Next in thread:**Joel Amzallag: "Re: [SI-LIST] : Diode Modeling"**Reply:**Joel Amzallag: "Re: [SI-LIST] : Diode Modeling"

Dear All:

In my recent post, the third paragraph includes:

"IBIS specs [Reference 1] require for the [POWER Clamp] data to be Vcc

relative, as illustrated by Figure 3 which is a plot of current through D2

versus Vcc-Vx. A comparison of Figures 2 and 3 reveals a shift of I(D2) from

the first to the second Cartesian quadrant."

D2 should have been D1.

Also the I-V table of XTK diode example includes typographical error. The

POINTS should be replaced by POINT as corrected below:

#Schottky diode to 5.0 Volts

LOADSPEC FAST_SCHOTTKY5

CEFF: 0

V-I: 5 POINTS

# Voltage given in Volts, Current in mA

POINT V: 0 I: 0

POINT V: 5.0 I: 0.0

POINT V: 5.5 I: 3.0

POINT V: 5.6 I: 5.0

POINT V: 5.75 I: 30.0

#End of Model

Best Regards,

Abe

----- Original Message -----

From: abe riazi <ariazi@serverworks.com>

To: <si-list@silab.eng.sun.com>

Sent: Friday, March 30, 2001 7:35 PM

Subject: [SI-LIST] : Diode Modeling

Dear Scholars:

The diode's PN junction and the base-emitter (or base-collector) junctions

of bipolar transistors are governed by similar physical laws. Subsequently,

diode model having numerous applications is regarded as fundamental to

models of other semiconductor devices. Several stages of creating IBIS,

SPICE and XTK diode models are described by this message.

IBIS model of a diode can be generated via simulation or measurements.

Figure 1 is schematic for generating behavioral model of 1N4002 rectifier

diode by way of simulation. Using PSPICE program, DC sweep was carried out

from -15 to +15V to cover the (-Vcc to 2Vcc) voltage range recommended by

IBIS specs.

Figure 2 presents simulation results for diode currents I(D1) and I(D2) as

function of applied voltage. When generating I-V (or V-T) curves for an

IBIS datasheet, higher accuracy is achievable by sampling more data points

in the non-linear regions (such as knee areas ) of the curve as opposed to

more linear sections . IBIS specs [Reference 1] require for the [POWER

Clamp] data to be Vcc relative, as illustrated by Figure 3 which is a plot

of current through D2 versus Vcc-Vx. A comparison of Figures 2 and 3 reveals

a shift of I(D2) from the first to the second Cartesian quadrant.

A diode IBIS model can be produced by extracting the [POWER Clamp] table

from I(D1) vs. (Vcc-Vx) of Figure 3, the [GND Clamp] data from I(D2) Vs. Vx

of Figure 2, incorporating package/pin parasitic values, and inserting the

necessary keywords [Reference 1] such as [IBIS Ver], [File Name], [File

Rev], [Component], [Manufacturer], etc.

Regarding procedure for creating SPICE diode macromodels, the major steps

[Reference 2] include: (i) Inspecting device data sheet for useable

modeling information. (such as, plots of forward diode current vs. voltage,

junction capacitance vs. diode voltage, etc.), (ii) conducting I-V and C-V

measurements to extract remaining parameter values, and (iii) performing

simulations to optimize model parameters.

The SPICE diode macromodel can contain fourteen parameters: IS (Reverse

leakage current), RS (Diode series resistance), N (Emission coefficient), BV

(diode breakdown voltage), IBV (Diode breakdown current), CJO (Zero-bias

junction capacitance), VJ (Bulk junction potential), FC (Coefficient for

capacitance), M (Grading coefficient), TT (transit time), EG (Energy

band-gap), XTI (Temperature coefficient), KF (Flicker-noise coefficient),

and AF (Flicker-noise exponent)). Each of above parameters has a default

value assigned by SPICE program; however, it is frequently possible (based

on application) to produce a sufficiently accurate diode model using just a

subset of the 14 parameters. For instance, parameters KF, AF, EG and XT1 are

needed only for AC noise analyses and temperature sweeps; hence, unnecessary

if the diode model is intended for other types of simulations. As another

example, SPICE model of a 1N4002 diode suitable for numerous applications

[Reference 2] includes:

IS = 46.5Pa, RS=123MohmS, N=1.35, CJO=51.5pF, M=0.333, VJ=0.381, FC=0.5,

TT=5.77uS.

(with remaining parameters at default values).

It should be added that SPICE model parameters are scalar variables of diode

equation:

Id = IS * [exp(qVd/Nkt) - 1]

Where Id is diode DC current, q is electron charge, Vd is voltage across

diode, K is Boltzmann's constant, and t is the diode temperature in degrees

Kelvin ( IS and N as defined earlier).

Different forms of above equation exist (some being approximations) for

describing three regions of diode operation namely: forward conduction,

reverse conduction before breakdown, and reverse-bias breakdown .

SPICE or IBIS models can not be directly utilized by some simulators. For

instance, XTK requires that models be in Quad format. A Quad diode model

can be created from the IBIS version using IBIS2XTK, or written manually.

A sample is presented:

#Schottky diode to 5.0 Volts

LOADSPEC FAST_SCHOTTKY5

CEFF: 0

V-I: 5 POINTS

# Voltage given in Volts, Current in mA

POINTS V: 0 I:0

POINTS V: 5.0 I:0.0

POINTS V: 5.5 I:3.0

POINTS V: 5.6 I: 5.0

POINTS V: 5.75 I: 30.0

#End of Model

The above discussed models have contained data limited to only one

simulation corner, whereas a more complete model demands data for three

(i.e. MIN, TYP and MAX) corners. Simulations results based on TYP models

are often well suited for purpose of correlation with physical measured

data. However, Fast and Slow corner runs are also frequently necessary to

verify a design under all conditions.

A finished model also needs a package/pin parasitic section. Nevertheless,

a model may lack parasitic portion mainly due to two reasons: (1) the model

developer leaves it to the user to ascertain what package type and parasitic

values are applicable, and (2) The model is intended for use at low

frequencies where parasitics have negligible effects.

In conclusion, several phases of generating IBIS and SPICE diode models were

explained. A XTK model was also exemplified to emphasize that some

simulators do not directly employ IBIS or SPICE models and demand

translation to simulator's native model format. One logical order for diode

modeling consists of first creating SPICE diode via measurements, then IBIS

model by means of simulation and finally the Quad version using IBIS2XTK.

REFERNCES:

1. IBIS (I/O Buffer Information Specification) Version 3.2, August 1999.

2. R. Kielkowski, "SPICE Practical Device Modeling", McGraw-Hill, Inc. 1995.

Your response is highly appreciated.

Respectfully,

Abe Riazi

ServerWorks

2251 Lawson Lane

Santa Clara, CA 95054

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**Next message:**Ingraham, Andrew: "RE: [SI-LIST] : Nyquest Sampling Rate"**Previous message:**Daniel, Erik S.: "RE: [SI-LIST] : Nyquist Sampling Rate"**In reply to:**abe riazi: "[SI-LIST] : Diode Modeling"**Next in thread:**Joel Amzallag: "Re: [SI-LIST] : Diode Modeling"**Reply:**Joel Amzallag: "Re: [SI-LIST] : Diode Modeling"

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