[SI-LIST] : IC packaging modelling in IBIS

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From: Perry Qu (perry.qu@alcatel.com)
Date: Thu Mar 29 2001 - 13:49:42 PST


Hi!

I had a question about packaging modelling in IBIS. In the version
before 3.2, we used lumped RLC for the traces/bonding wires on the
substrate. In the 3.2 specification, I found that there are both
per-unit-length RLC definition and matrix RLC definition in .pkg
section. My question is, as the digital signal goes faster and faster,
shall we model the packaging traces as transmission lines ? And how do
we do that in IBIS 3.2 ?

A related question is the electrical design of IC packaging. For high
speed ASIC with large BGA packaging, do packaging vendors consider
impedance control on their substrate ?

Thanks in advance.

Perry Qu



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