**From:** Scott McMorrow (*scott@vasthorizons.com*)

**Date:** Thu Mar 29 2001 - 03:41:50 PST

**Next message:**Peterson, James F (FL51): "[SI-LIST] : adjacent planes.....sort of"**Previous message:**KokTongTHAM: "[SI-LIST] : non-monotonic"**In reply to:**wayne.nunn@philips.com: "[SI-LIST] : Plating Tails at High Frequencies"

wayne,

I'm back from vacation!

Actually, there is current flowing through the plating tails. From a purely

transmission line standpoint, the tail is a transmission line stub hanging

out off the via. For example, when a wave edge is launched from the die,

when it reaches the ball via, there are two paths it can take. One down the

ball to the PCB trace, and the other down the plating tail. The wavefront does

not know apriori that the plating tail is not connected to it. That wave will split,

part going down the ball path and part going down the plating tail path, based

upon the relative impedance of both paths. Should they have nearly equal

impedance, then half of the wave will travel along the plating tail until it hit the

end (which is an infinite impedance) and reflect back with a reflection coeficient

of 1. Since there is wave propagation, there is current flow.

The effect of the plating tail will depend upon its electrical length relative to

the risetime and frequency components of the signals being driven off the die.

Since some plating tails can easily be over 250mils in length or more, they can

present significant discontinuities to fast edge rate or high frequency signals. For

example, a trace in BT epoxy and encapsulated in plastic has a velocity of

propagation of about 180 to 200ps per inch. So, a 250mil plating tail would have

an electrial length of 45ps. The end of the tail would not be "seen" by waveforms

passing through the ball until one round trip or 90ps after the first incident waveform

arrives. That plating tail would also exhibit a quarter wave resonance at 5 GHz, and

would have an adverse effect on OC48 (2.5Gbps) data streams. At lower data rates,

it will cause jitter and edge distortion of the signal transmitted through the package.

To approximate the plating tail as just a capacitor misses the fact that it as a

waveguide stub.

Also, for those interested, multiple plating tails of the same length (and there are many

in a package) will be tuned to the same resonant frequency. They can actually

"sing" together if excited with fast enough edges, or high enough data rates. A full wave

simulation can show these sorts of eigenmodes ... at least for simplified cases.

best regards,

scott

-- Scott McMorrow Principal Engineer SiQual, Signal Quality Engineering 18735 SW Boones Ferry Road Tualatin, OR 97062-3090 (503) 885-1231 http://www.siqual.comwayne.nunn@philips.com wrote:

> In a PBGA substrate there are plating tails that project from the last via to ball connection to the edge of the substrate. Since there is no current flowing through these traces, inductance shouldn't be a problem at any frequency. Are there capacitive > issues at high frequencies, say above 500mHz? > > Thanks, > > --Wayne > ------------------------------------------------------------------------------------------------------------- > Philips Semiconductors - ATO Innovation San Jose > Wayne A. Nunn > Staff Engineer > > 1101 McKay Drive > San Jose, Ca 95131 < Voice: 408.474.5620 Fax: 408.474.5505 > > ------------------------------------------------------------------------------------------------------------ > > **** To unsubscribe from si-list or si-list-digest: send e-mail to > majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE > si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP. > si-list archives are accessible at http://www.qsl.net/wb6tpu > ****

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**Next message:**Peterson, James F (FL51): "[SI-LIST] : adjacent planes.....sort of"**Previous message:**KokTongTHAM: "[SI-LIST] : non-monotonic"**In reply to:**wayne.nunn@philips.com: "[SI-LIST] : Plating Tails at High Frequencies"

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