[SI-LIST] : internal timestep too small in transient analysis

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From: Elias Lozano (elias@nband.com)
Date: Fri Mar 23 2001 - 16:05:00 PST


I have a question,
 
I am having a lot of trouble with this error when doing signal integrity
simulations of some I/O buffers with package models and T models for
tranmission lines as well as some loading. I am using HSPICE2000 version. I
will change to U and then W models for more accuracy.
 
I would like to get a fresh look at what are the best options to use when
having this problem.
In the past, I have had the same problem with TSMC 0.18um models due to some
negative-mos conductances?
Is there anyone out there experiencing the same problem and if so any ideas
on how to find the right set of options so that I don't get these erros?
 
Once again this is what I am simulating:
 
 
I/O buffer + Package model + Tmodel + capacitive loading
 
I appreciate any comments.
 
Regards
 
Elias

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