RE: [SI-LIST] : How to model effect of vias on nearby traces?

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From: Haller, Robert (rhaller@cereva.com)
Date: Fri Mar 23 2001 - 05:49:23 PST


Larry and Patel,
        I also was curious about this, so I designed and built a test board
(a few years ago). There was a few things I found out and a few things
that went unanswered. I am working from memory so results are general.

First I created some control lines to measure critical electrical
parameters.
Second I routed etch through the center of connector and BGA fields.
Third I partially off-set the etch through the connector and BGA fields to
mimic what would happen with layer to layer mis-registration (the designed
etch routed partially over the anti-pad of the adjacent plane). Fourth I
offset the etch an entire line width over the anti pad. Finally I routed
off-set etch through a BGA field and serpentine'd the etch to stay
completely
in the BGA field. All of the etch lengths and widths were the same and on
the same layer to minimize manufacturing inconsistencies.

I used a TDR with a 40 Ps edge to look at Characteristic Impedance, and Prop
delay.
I also launched representative signals (100ps edges) down the lines and
observed
the impact (reflections, delay) on them.

What I found somewhat surprised me. The first four experiments exhibited
small
variations in characteristic impedance (Like you pointed out Larry),but
noticeable
bumps in the TDR traces. The propagation delay was within measurement
accuracy
(homogenous dielectric constant). The only exception was the final
experiment
where the entire line was in the BGA field and routed partially over the
Anti-pads.

I concluded that you don't serpentine etch in bga or connector fields.
I do not advocate routing etch over anti-pads, although I was surprised
it was not as bad I expected. But, I did not look at return currents and
increased loop inductance which is of concern in a complete circuit
especially if lots of outputs are switching. I did not look at crosstalk
impact.

Regards,
Bob Haller
cereva Networks
rhaller@cereva.com
508-787-5365

-----Original Message-----
From: Larry Miller [mailto:ldmiller@rhapsodynetworks.com]
Sent: Thursday, March 22, 2001 4:42 PM
To: 'Patel, Bhavesh'; SI_LIST (E-mail)
Subject: RE: [SI-LIST] : How to model effect of vias on nearby traces?

I have seen some high speed connector TDR plots where traces are routed
through pin fields on back/midplanes. This is similar to passing near a via,
even worse I would think. I have also done TDR's on our own boards.

The effect seems to be very small (a few % of 50 ohms) and of short duration
in time, which of course corresponds to very high frequencies (10's of GHz).

One view.

Larry Miller

-----Original Message-----
From: Patel, Bhavesh [mailto:bpatel@cyras.com]
Sent: Wednesday, March 21, 2001 8:06 PM
To: SI_LIST (E-mail)
Subject: [SI-LIST] : How to model effect of vias on nearby traces?

Hi! I wanted to know how do I simulate the effect on the impedance..
reflection on a trace/signal when it is very close to a via. It does not go
thru the via but passes very close to it. Can I model this in HSPICE? And if
yes how/
Thanks in advance
Bhavesh

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