RE: [SI-LIST] : specctraquest timing question

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From: Bill Chen (bchen@razafoundries.com)
Date: Tue Mar 20 2001 - 15:56:45 PST


Hi Scot,

    SpecctrQuest can generate 'flight time' delay number due
to system interconnects and loading by automatically compensating
buffer delay under the test load. So if your IBIS model test
fixture loading is the same as your Tco datasheet reference load,
the tool can do the calculation for you. However, if your IBIS model
test load is not the same as the datasheet reference load given by
the vendor, you need to do one of the following:
1) Run two simulations one with datasheet test load and the other with
   system load (interconnects and loading). Then do the calculation:

     Tdelay_clk_to_receiver_pin =
                  Tco - Tdelay_under_testload + Tdelay_system_load
2) Modify the IBIS test fixture, redo buffer delay calculation and
   do simulation
   
      Tdelay_clk_to_receiver_pin = Tco + Tdelay_adjusted

     Please note the Tdelay_adjusted may be a negative number.

As far as what to use between the "switch delay" and the
"settle delay", it depends. Switch delay for rise edge is
measured at first Vil crossing and for falling edge it
is measured first crossing at Vih. Settle delay for rise
edge is measured at the final Vih crossing and for falling
edge it is measured at the final Vil crossing.
For more conservative calculation, use worst settle delay for your
maximum delay calculation, and use best switching delay for your
min delay calculation. Or you can configure SpecctraQuest to report
delay numbers based on specific Vm measurement point.

Hope this helps!

Bill Chen, Ph.D.

Raza Foundries Inc
www.razafoundries.com

-----Original Message-----
From: Sampson, Scot [mailto:ssampson@sonusnet.com]
Sent: Tuesday, March 20, 2001 11:17 AM
To: 'si-list@silab.eng.sun.com'
Subject: [SI-LIST] : specctraquest timing question

 Hi All

We are in the process of trying to perform timing analysis
based on specctraquest simulations to determine if we are in good bad
or other territory. At the start of this exercise the engineer
has a clock to out number that is made up of a clock to buffer
input delay and then a buffer delay into a test load. From the
simulations we have the delay of the buffer driving the desired
net. What we desire is the clock to receiver input number. At
a high level, this appears to be the clock to out number, minus
the buffer into the test load, plus the driver into the receiver in
question. Is the last of these three terms merely the worst of
switchrise+risedly or switchfall+falldly? Is the only way to get
the buffer into testload number running a sim with the buffer and
test load? Is the timing number we are looking for merely the
clock to out number plus the worst of settlerise/settlefall delay?

 Thanx for the help

 Scot

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