**From:** *rich.evans@st.com*

**Date:** Tue Mar 20 2001 - 07:51:36 PST

**Next message:**Perry Qu: "[SI-LIST] : alternative SPICE tool"**Previous message:**Ken Cantrell: "RE: [SI-LIST] : Re: approximations for partial self inductance - WHY"

Michael, thank you for the very clear discussion.

After many hours (years?) of messing with inductances, I

must agree completely with Michael. Partial inductance

can be useful, but it's very dangerous.

best regards to all

Rich

----------------------------------------------------------------------

Sainath, I used to believe as you do, that partial inductances are

useful to obtain some first-cut answers. Over the years, I've changed

my mind. I believe that the potential for misuse from partial

inductances outweighs their benefits, and I'm now doing all my signal

integrity modeling with loop inductances. I'm much happier. :-)

Here are some of the problems I see with partial inductances: 1.)

They are arbitrary; as Brian Young points out in his wonderful new

book, you can add any constant you want to the partial inductance

matrix without changing the physical result. Different techniques for

calculating partial inductance give different answers --- witness the

discussion we've just had on this point. 2.) When you use partial

inductances in SPICE simulations, they give you things that look like

"ground bounce": voltage differences across large sections of your

circuit, where it is impossible to make a unique physical measurement

of voltage because of linked flux. Brian Young again points out that

ground bounce is not unique; it depends on your definition of partial

inductance. You can be mislead by how chip ground is bouncing with

respect to module ground in your simulation --- it looks like

something real, but it's not. When you use loop inductances, and use

SPICE node 0 to represent local reference everywhere, you can't be

mislead; there's no node voltage in your simulation that looks like

ground bounce. 3.) If you use partial inductances in your SPICE

simulations, you have to make sure that all the current in your

simulation moves from one side of your circuit to the other only

through the partial inductances. If you have node 0 on both sides,

for example, you've violated the assumptions under which partial

inductance is valid. And it can be very hard to avoid node 0

sometimes, and it appears that having large sections of your circuit

isolated from node 0 makes convergence more difficult. 4.) Partial

inductances are completely invalid without mutual inductances, but

there's a great tendency to ignore them as a "first-pass engineering

assumption". This is natural; all of engineering is about ignoring

things. :-) But it just doesn't work with partial inductances. At

best, you're making assumptions about where the return path is (and

different ways of calculating partial inductances make different

assumptions); at worst, you miss the entire point of the exercise.

Without partial mutual inductances, there's no reason to put power and

ground planes close to each other. Basically, my feeling now is that

partial inductances are a wonderful tool for calculating inductance in

the standard signal integrity situation where the full loop is not

completely known (package without chip or board, for example). But I

think now they should remain a computational tool, and that the models

that are eventually generated should be based on loop inductances.

I'm working on a paper explaining these points in more detail and

talking about how we've been using loop inductance rather than partial

inductance for package modeling here at Compaq. I hope to present the

paper at EPEP'01 here in Massachusetts. I would appreciate any

comments people might have.

--

Michael Tsuk

Compaq AlphaServer Product Development

(508) 467-4621 -----Original Message-----

From: Sainath Nimmagadda [mailto:sainath@lsil.co

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