**From:** Ken Cantrell (*[email protected]*)

**Date:** Tue Mar 20 2001 - 07:37:28 PST

**Next message:**[email protected]: "[SI-LIST] : Partial inductance...."**Previous message:**Larry Miller: "RE: [SI-LIST] : Jitter measurement"**In reply to:**Tsuk, Michael: "RE: [SI-LIST] : Re: approximations for partial self inductance - WHY"**Next in thread:**Sainath Nimmagadda: "Re: [SI-LIST] : Re: approximations for partial self inductance - WHY"

Michael,

Sounds very interesting. Can you post your presentation somewhere for those

of us who can't make the EPOP'01?

Thanks,

Ken

-----Original Message-----

From: [email protected]

[mailto:[email protected]]On Behalf Of Tsuk, Michael

Sent: Tuesday, March 20, 2001 6:54 AM

To: 'Sainath Nimmagadda'; [email protected]

Cc: Mike Jenkins; 'Brian Young'

Subject: RE: [SI-LIST] : Re: approximations for partial self inductance -

WHY

Sainath,

I used to believe as you do, that partial inductances are useful to obtain

some first-cut answers. Over the years, I've changed my mind. I believe

that the potential for misuse from partial inductances outweighs their

benefits, and I'm now doing all my signal integrity modeling with loop

inductances. I'm much happier. :-)

Here are some of the problems I see with partial inductances:

1.) They are arbitrary; as Brian Young points out in his wonderful new

book, you can add any constant you want to the partial inductance matrix

without changing the physical result. Different techniques for calculating

partial inductance give different answers --- witness the discussion we've

just had on this point.

2.) When you use partial inductances in SPICE simulations, they give you

things that look like "ground bounce": voltage differences across large

sections of your circuit, where it is impossible to make a unique physical

measurement of voltage because of linked flux. Brian Young again points out

that ground bounce is not unique; it depends on your definition of partial

inductance. You can be mislead by how chip ground is bouncing with respect

to module ground in your simulation --- it looks like something real, but

it's not. When you use loop inductances, and use SPICE node 0 to represent

local reference everywhere, you can't be mislead; there's no node voltage in

your simulation that looks like ground bounce.

3.) If you use partial inductances in your SPICE simulations, you have to

make sure that all the current in your simulation moves from one side of

your circuit to the other only through the partial inductances. If you have

node 0 on both sides, for example, you've violated the assumptions under

which partial inductance is valid. And it can be very hard to avoid node 0

sometimes, and it appears that having large sections of your circuit

isolated from node 0 makes convergence more difficult.

4.) Partial inductances are completely invalid without mutual inductances,

but there's a great tendency to ignore them as a "first-pass engineering

assumption". This is natural; all of engineering is about ignoring things.

:-) But it just doesn't work with partial inductances. At best, you're

making assumptions about where the return path is (and different ways of

calculating partial inductances make different assumptions); at worst, you

miss the entire point of the exercise. Without partial mutual inductances,

there's no reason to put power and ground planes close to each other.

Basically, my feeling now is that partial inductances are a wonderful tool

for calculating inductance in the standard signal integrity situation where

the full loop is not completely known (package without chip or board, for

example). But I think now they should remain a computational tool, and that

the models that are eventually generated should be based on loop

inductances.

I'm working on a paper explaining these points in more detail and talking

about how we've been using loop inductance rather than partial inductance

for package modeling here at Compaq. I hope to present the paper at EPEP'01

here in Massachusetts. I would appreciate any comments people might have.

-- Michael Tsuk Compaq AlphaServer Product Development (508) 467-4621-----Original Message----- From: Sainath Nimmagadda [mailto:[email protected]] Sent: Monday, March 19, 2001 9:59 PM To: [email protected] Cc: Mike Jenkins Subject: Re: [SI-LIST] : Re: approximations for partial self inductance - WHY

Dear Mike, Good point. Strictly speaking and from a closed solution (analytical) point, we should not attach any physical significance to individual partial inductances. But, from a discretized solution (computational) point - which is the way we are being driven by technology, such as the finite-difference time-domain for example, is it not a mathematical convenience to consider those individual partial inductances - especially where one does not know how and where the current loops are closing - to obtain some first-cut answers? Just another view.

Regards, Sainath

Mike Jenkins wrote:

All, FWIW, I recall that the IBM Yorktown researchers who developed the partial inductance concept included on the first page of the research report the quote from Weber to the effect that inductance makes no sense unless one considers the entire loop of current. I guess they were sensitive to not inducing readers to attach any physical significance to the individual partial inductances.

Regards, Mike

"Tsuk, Michael" wrote: > > Doug McKean wrote: > > ------------------------------------------------------------ > Okay, well here goes ... > > It's easy to see that if a signal trace had a return trace as a > wire (shown by a dotted line), the following would cause > the creation of a loop. > > | > | > | > +----------+ > . | > return . | signal > trace . Loop | trace > . | > +----------+ > | > | > | > > Obviously from this construction, the inductance of the > return wire would be less than if the return wire was > underneath and following the longer path of the signal > trace. Thus, my questioning the path of less inductance > rule. > > ------------------------------------------------------------ > > The confusion comes from the fact that you've ignored mutual inductance > here, which acts to reduce the total inductance of this circuit. The return > current will choose the path (or combination of paths) that minimize the > *total* loop inductance, not the partial inductance of the return alone. > > In general, you can never ignore mutual inductance. :-( This is > particularly true if you're dealing with partial inductances, which are only > useful if all mutuals are included. > > Even more interesting to my mind is the sign error you made in calculating > the direction of the magnetic force on your currents. The magnetic force > between two parallel currents draws them *together* if the currents are in > the same direction, and pushes them *apart* if they are in opposite > directions. Check any electromagnetics text. Your mistake is that you > assumed a *positive* charge when you equated the current direction with the > velocity of your particle, but a *negative* charge when you calculated the > force. > > Why the apparent effect of minimizing inductance works in the opposite > direction is very interesting. I think I have the answer, but I'm not sure. > I'd appreciate any input people might have. > > -- > Michael Tsuk > Compaq AlphaServer Product Development > (508) 467-4621 > > -----Original Message----- > From: Doug McKean [mailto:[email protected]] > Sent: Monday, March 19, 2001 4:08 PM > To: si-[email protected] > Cc: Doug McKean > Subject: Re: [SI-LIST] : Re: approximations for partial self inductance > - WHY > > ------------------------------------------------------------ > Okay, well here goes ... > > It's easy to see that if a signal trace had a return trace as a > wire (shown by a dotted line), the following would cause > the creation of a loop. > > | > | > | > +----------+ > . | > return . | signal > trace . Loop | trace > . | > +----------+ > | > | > | > > Obviously from this construction, the inductance of the > return wire would be less than if the return wire was > underneath and following the longer path of the signal > trace. Thus, my questioning the path of less inductance > rule. > > As shown above, the signal current path forms the bottom, > right side, and top parts of a loop. The return current path > forms the left side of the a loop. > > Assume the signal path is bound one-dimensionally by the > confines of the trace. Assume the return path is bound two > dimensionally by the confines of the ground plane. In other > words, the signal path is not free to move at all, but the > return path is free to move in 2-D (up, down, left, right > in the above picture). > > Now, assume the return path in the ground IS as shown above > with the signal path and the return path. We have a loop. The > virtual current loop if you will, circulates causing a soloenoidal > action creating a magnetic field in the center. As such, using > the right hand rule for current vs. magnetic fields, we have a > magnetic field coming out of the monitor. The magnetic field > lines are normal to the screen of the monitor. > > Using the other right hand rule for charges moving in a magnetic > field by way of the Lorentz force, my thumb points in the direction > of current flow, my fingers point in the direction of the magnetic > field, and my palm points in the direction that the a positive > charge would be pushed. With a negative charge, the push is > from the back of your hand or toward the signal wire. Since > the return current is bound only by a plane, it seeks to be > under the signal trace. And it would continue to balance > itself there. > > Turn the path of the signal current around and the return > current, everything reverses including the direction of the > magnetic field, and we still have a Lorentz force pusing the > return current back to the signal trace. > > A DC return current in the ground plane wouldn't cause such > action. It would follow only the path of least resistance. > > This is lots more wordy than if I was face to face and showed > with the right hand rule for negative charge in a magnetic field. > > Regards, Doug McKean > ------------------------------------------------------------ > > **** To unsubscribe from si-list or si-list-digest: send e-mail to > [email protected] In the BODY of message put: UNSUBSCRIBE > si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP. > si-list archives are accessible at http://www.qsl.net/wb6tpu > **** > > **** To unsubscribe from si-list or si-list-digest: send e-mail to > [email protected] In the BODY of message put: UNSUBSCRIBE > si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP. > si-list archives are accessible at http://www.qsl.net/wb6tpu > ****

-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Mike Jenkins Phone: 408.433.7901 _____ LSI Logic Corp, ms/G715 Fax: 408.433.7495 LSI|LOGIC| (R) 1525 McCarthy Blvd. mailto:[email protected] | | Milpitas, CA 95035 http://www.lsilogic.com |_____| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

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**Next message:**[email protected]: "[SI-LIST] : Partial inductance...."**Previous message:**Larry Miller: "RE: [SI-LIST] : Jitter measurement"**In reply to:**Tsuk, Michael: "RE: [SI-LIST] : Re: approximations for partial self inductance - WHY"**Next in thread:**Sainath Nimmagadda: "Re: [SI-LIST] : Re: approximations for partial self inductance - WHY"

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