RE: [SI-LIST] : Layout of Bypass Cap

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From: Larry Smith (ldsmith@lisboa.eng.sun.com)
Date: Mon Mar 19 2001 - 09:58:21 PST


Andy - I completely agree with you. In these days, it is impossible to
determine which individual decoupling capacitor is supplying current to
a uP or ASIC that demands current. There may be 100's of discrete
capacitors, all of which contribute current at some frequency.

The power distribution problem has two parts: 1) power distribution
system (PDS) impedance at the printed circuit board level and 2)
inductance for the power consumer (chip). The PDS impedance is managed
through the entire frequency spectrum by the voltage regulator module,
bulk caps, high frequency caps and power plane characteristics. The
best you can hope for is a low impedance PDS up to the frequency of
interest, probably 100 MHz or more. A power consumer mounted on the
power planes should look out and see this low impedance. It is
impossible to say which individual components supply the current unless
a specific frequency is specified.

Below about 100 MHz, the PDS impedance is determined by the RLC
characteristics of the mounted decoupling capacitors. The mounting
inductance and the ESR of capacitors are of primary importance here.
Many different combinations of components and mounting structures can
be used as long as the resulting impedance is sufficiently low and flat
across the entire frequency range. The design with the minimum
mounting inductance for the capacitors will have the minimum number of
components. An impedance peak in the PDS at any particular frequency
will cause ringing during a power transient and resonance problems if
the system ever happens to be stimulated at the peak frequency.

Above about 100 MHz, the power distribution impedance is basically
determined by the power planes. All the decoupling capacitors in the
world will not do any good unless there is a sufficiently low impedance
channel that attaches them to the power consumer. That is the role of
the power planes. They provide capacitance as well as the low
impedance hook up. A thinner the power plane dielectric gives a lower
impedance as well as more capacitance.

Once a sufficiently low impedance PDS has been established, the next
important thing is the loop inductance between the power consumer (uP
or ASIC) and the PDS. There is inductance in the electronic package
that carries the chip. With good package design (many pairs of Vdd and
Gnd bumps, wire bonds, balls, vias, etc) it is possible to get the
mounting inductance of the chip well below 100 pH. If this is the
case, the PCB power plane spreading inductance probably dominates the
loop inductance between the PDS and the chip. Once again, the best way
to manage this is with thin dielectric power planes. Power planes do
provide decoupling capacitance at high frequency. But their most
important roll for high power delivery systems at high frequency is
their impedance (inductance). In this case, the thinner the dielectric,
the better.

I like to think of this as a two part problem. The first goal is to
establish a low impedance PDS at the PCB level. The second goal is to
hook up the power consumer to the PDS. The PCB power planes play a
very important role in both parts.

regards,
Larry Smith
Sun Microsystems

> From: "Ingraham, Andrew" <Andrew.Ingraham@compaq.com>
> To: "'si-list'" <si-list@silab.eng.sun.com>
> Subject: RE: [SI-LIST] : Layout of Bypass Cap
> Date: Fri, 16 Mar 2001 14:29:24 -0500
>
> > In any case your goal is to minimize the inductance between the cap and
> > the
> > IC,
>
> I would say the preferred goal is to minimize the inductance between the IC
> and the plane!
>
> The plane is usually your best high frequency bypass capacitance, though
> small. The discrete cap fills in when the local plane capacitance in that
> area starts to be depleted.
>
> Do not make longer traces to get a direct connection from the IC pin to the
> cap. But not everyone agrees.
>
> Andy
>
>
>
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