RE: [SI-LIST] : Layout of Bypass Cap

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From: S. Weir (weirsp@atdial.net)
Date: Sat Mar 17 2001 - 16:26:42 PST


Michael,

I believe that you are mistaken in your premise and conclusion. Yes, two
vias make for 2X the inductance, but this only matters if the underlying
premise is that the highest frequency current loop includes the
capacitor. With any reasonable power and ground plane pair, the highest
frequency loop is in series with the parallel plate capacitance of the
planes, in parallel with the LC network formed by the decoupling capacitors
and their respective interconnects to the planes. This is well documented
in literature by Dr. Johnson, and papers repeatedly referred to here by the
folks at SUN.

Regards,

Steve.
At 01:49 PM 3/16/01 -0500, you wrote:
>si-list@silab.eng.sun.com

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