**From:** Itzhak Hirshtal (*[email protected]*)

**Date:** Fri Mar 16 2001 - 02:54:30 PST

**Next message:**Peterson, James F (FL51): "RE: [SI-LIST] : Book questions."**Previous message:**Grossman, Brett: "RE: [SI-LIST] : Re: approximations for partial self inductance"**In reply to:**John Lipsius: "RE: [SI-LIST] : Inductance and Decoupling"

Hello, John

It seems intuitively that you are right, but let's consider other factors

that might change your opinion:

(1) When you use vias, you actually add inductance. If we take the equations

for partial self inductance of a via we have more than 0.5nH for each. e.g.:

let's take via length to be 60mil and its radius to be 6mils. Then from

Bogatin's (and Young's) equation for partial self inductance of a via you get

app. 0.7nH. From Bogatin's equation from his paper on chipscale package

inductance for the mutual inductance between 2 parallel wires you get app.

0.15nH for a separation of 50mil between any 2 vias. So effectively each via

has an inductance of (0.7-0.15=)0.55nH. When you multiply this by 4 (you have

to get out of the capacitor twice and the same is true for the supplied

device also) then you already have 2.2nH. And that's true only if the vias

are real close! Otherwise, the total inductance is closer to the self

inductance.

(2) It's true that the loop area of the supply current is minimized on

adjacent planes, but for this case it is too short and can only reduce the

inductance outside the vias path. Anyway you get more inductance, even if

it's very small.

(3) On the other hand, if you can get the capacitor to be close enough to the

supply pins and connect it using a relatively wide traces, then you can

reduce the total inductance. For example, a capacitor 50mil distant from the

supply pins and connected with a 35mil wide trace to both vdd and gnd pins

will yield a total inductance of 0.8nH. I use here an equation for the

partial self inductance of a rectangular trace from the same paper, mentioned

above, by Bogatin which is: L=5*d*[ln(2d/w+t) + 0.5]nH, where d is length of

trace and w is its width and t is its hight, all in inches. The equation

yields less than 400pH for each connection for the above conditions. I admit

that it is difficult to achieve such proximities in general, but that does

not ease the practical problem we face.

(4) And now, with these updated calculations I get even worse results than in

my first email: Up to 100 capacitiors are needed using vias, or 30 if you

manage to place them close enough!

The bottom line here, do I miscalculate or misunderstand something? Or is the

situation really so bad? If so, then how come that most designs (for the best

of my knowledge) work with much less than my calculated number of capacitors?

Remember that in my first email I had not even counted in the internal

sources of current change of a device, just its external bus(es)!

John Lipsius wrote:

*> Itzhak,
*

*>
*

*> re: item 2, decap (decoupling cap) inductance. My understanding
*

*> from actual characterization I saw done and the si-list, is that
*

*> traces from decap to vdd pin is inherently inferior to just
*

*> taking vias to vdd plane (likewise for decap gnd).
*

*>
*

*> Your results notwithstanding, by definition the L for the
*

*> decap w/ vias straight to planes must always be less than when
*

*> connecting to vdd pin, since the loop area is thus minimized.
*

*>
*

*> When you instead connect decap to vdd pin then this theory says you put
*

*> much more L in series with the chips supply than with the via-to-plane
*

*> situation, defeating the broadband filtering intent if it's done for many
*

*> or all decaps.
*

*>
*

*> > -----Original Message-----
*

*> > From: Itzhak Hirshtal [mailto:[email protected]]
*

*> > Sent: Monday, March 12, 2001 6:33 AM
*

*> > To: si-list
*

*> > Subject: [SI-LIST] : Inductance and Decoupling
*

*> >
*

*> >
*

*> > Hello, all
*

*> >
*

*> > I've recently started to calculate the de-coupling needed for
*

*> > efficiently supplying the spike currents needed by high-speed devices.
*

*> > During this task, I've encountered several ambiguities and
*

*> > results that
*

*> > I would like to share with you and perhaps hear some (useful) feedback
*

*> > from you.
*

*> >
*

*> > (1) I tried to evaluate the situation for one high-pin-count
*

*> > device with
*

*> > several buses connected to it (essentially a bus bridge). Even
*

*> > calculating for just one synchronous bus (with 144 bits overall) I
*

*> > arrived to the result that a few Amps (maybe even 5) are
*

*> > drawn when all
*

*> > or most of this bus bits change state. I wonder what will be
*

*> > the result
*

*> > if I would calculate for an additional bus (assuming it's synchronous
*

*> > with the first). And what about the internal changes? They might be
*

*> > contributing even more than the external bus! (e.g., the Motorola
*

*> > PowerPC HW manual states that 90% of the power consumption of this
*

*> > device is drawn internally, not externally).
*

*> >
*

*> > (2) I've also tried to calculate the inductance of the decoupling
*

*> > capacitors connections to the device. Even assuming a 40-mil
*

*> > wide 50-mil
*

*> > long trace right above a reference plane for the connection I
*

*> > have app.
*

*> > L=150-200pH. If I can't connect at least one of the capacitor pads so
*

*> > short I might have to do a direct connection via to a
*

*> > reference plane. I
*

*> > calculated this to have more than L=1nH!
*

*> >
*

*> > (3) I assumed the calculated peak currents change at a rate equivalent
*

*> > to the rise time of the device's output buffers. I don't know if it's
*

*> > true, but this seems to me the most logical thing to do. Even
*

*> > if I take
*

*> > it to be 2ns (1 ns is closer to worst-case, I believe), I get the
*

*> > result that I need 40 to 50 low-ESL decoupling capacitors for the case
*

*> > where L=1nH. Only if I succeed to connect the capacitors directly and
*

*> > close enough to both GND and VDD pins (L=150-200pH) do I get
*

*> > the result
*

*> > that it is sufficient to use 4-6 decoupling capacitors.
*

*> >
*

*> > (4) While calculating vias inductance, I've encountered 2 similar but
*

*> > different equations for this parameter. One is given by Mr. H. Johnson
*

*> > in his famous book (page 259), as follows:
*

*> >
*

*> > L=5d*{ln(2d/r)+1}nH.
*

*> >
*

*> > The other is given by Mr. Bogatin in one of his articles, and is:
*

*> >
*

*> > L=5d*{ln(2d/r)-3/4}nH.
*

*> >
*

*> > Can somwone explain the reason for the difference, or who is
*

*> > right? The
*

*> > difference starts to be quite critical when dealing with u-Vias!
*

*> >
*

*> > Thanks for anyone who makes the effort to read this email.
*

*> >
*

*> > --
*

*> > Itzhak Hirshtal
*

*> > Elta Electronics
*

*> > POB 330 Ashdod
*

*> > Israel 77102
*

*> > Tel: 972-8-8572841
*

*> > Fax: 972-8-8572978
*

*> > email: [email protected]
*

*> >
*

*> >
*

*>
*

*> **** To unsubscribe from si-list or si-list-digest: send e-mail to
*

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*

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*

*> ****
*

-- Itzhak Hirshtal Elta Electronics POB 330 Ashdod Israel 77102 Tel: 972-8-8572841 Fax: 972-8-8572978 email: [email protected]

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**Next message:**Peterson, James F (FL51): "RE: [SI-LIST] : Book questions."**Previous message:**Grossman, Brett: "RE: [SI-LIST] : Re: approximations for partial self inductance"**In reply to:**John Lipsius: "RE: [SI-LIST] : Inductance and Decoupling"

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