RE: [SI-LIST] : DIMM IBIS Model / Signal Integrity

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From: tcrondeau (tcrondeau@micron.com)
Date: Wed Mar 14 2001 - 11:17:44 PST


Bouchra,

First lets address the software that is known to handle EBD models. We have
been using Mentor Graphics ICX, Cadence Specctraquest, and HyperLynx is
coming out with a version that will handle the models as well. The ICX and
Specctraquest, tools all the user to pick the probe point to be displayed.
Let me describe a simulation for you.

Using a mother board as the MAIN board the model is loaded into the tool and
assigned to a DIMM slot in this case on the MAIN board. The DIMM becomes a
daughter card that is now part of the total system. For most signals the
driver will be the chip set. When the simulator is set to do a simulation it
will extract the information for the net to be simulated. This information
is going to come from the MAIN board design and the EBD model of the DIMM.
The EBD contains all the connectivity information about the DIMM including
the loads that are on the DIMM including IBIS models of loads. This
information is then used to complete the system net and is simulated. Most
of the tools will create probe points for all the loads and the driver of
the system net. The GUI used to display the waveform information then allows
the user to view what ever probe point is desired.

Yes the quality of the signal will include all or some reflection depending
on the location of the probe point. Please note that EBD models are not
coupled models. So cross talk contributions will not be counted for the
board that is represented by EBD. The time delay at each probe point should
represent a value very close to the actual time delay of the net.

Best regards,

Tom Rondeau
Simulation Engineer
Micron Technology, Inc.
tcrondeau@micron.com

-----Original Message-----
From: BIBICHA [mailto:f_bouchra@yahoo.com]
Sent: Wednesday, March 14, 2001 10:16 AM
To: si-list@silab.eng.sun.com
Subject: [SI-LIST] : DIMM IBIS Model / Signal Integrity

Hi all:
I would like to know if we give u an IBIS model or .EBD file of a DIMM.
That model will probably be attached to the pin of the connector. We are
interested to know how do u probe software wise what is the quality of the
signal and time delay at each pin of every device on the DIMM attached to
the net being simulated.
The quality of the signal at the pin of the connector for a net with many
devices attached to it like an Adress line, would be a cummulative effect of
all reflections from all devices attached. Probing at the Pin of the
connector will show a signal quality that is not representative of the
quality at the pin of each device attached to the net. Therefore, we would
like to know from you how do u differenciate between the signal of the net
at the pin of the connector from the signal at the pin of every device
attached to the net.

Any feedback will be greatly appreciated.

Bouchra

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