RE: [SI-LIST] : noise budgeting

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From: Larry Miller ([email protected])
Date: Wed Mar 14 2001 - 06:32:08 PST

I would think that RSSing would be very dicey unless you had some statistics
on the various noise components. If you do get an algebraically summed worst
case combination of noises in a digital system, you get an error! The RSS
calculations done in (say) fiber optics links are for miniscule error rates
in a system that by protocol can tolerate a certain amount of errors.
Perhaps you can design an error-tolerant system.

Generally it seems that a particular item on your list (reflections,
crosstalk, simultaneous switching noise) rears its ugly head in any
particular design and is dominant. If you get more than one of these causing
problems you are going to have a very bad day (or week or year). It gets
very difficult to separate the symptoms.

With high edge rates and wide parallel buses you have to fight hard on all
fronts and maybe that will not be enough. Defensive architecture can save
many headaches-- for example, using coded interfaces (8B/10B or similar) can
greatly reduce the probability of SSO problems if you expect to have data
with lots of zeroes or lots of ones, even though it makes the innards of an
ASIC more complex.

Crosstalk and reflections are layout problems, and the way to avoid them is
to do the layout right. Taking short cuts (cheating) just does not work.
"It's not NICE to fool Mother Nature" as an old commercial once said.
Actually, it's impossible.

As you said in your last paragraph, there are so many variables that a
general mathematical budget is next to impossible, except for a simple
network. Present day high speed designs are pushing the edge on practically
every front.

Larry Miller

-----Original Message-----
From: Perry Qu [mailto:[email protected]]
Sent: Wednesday, March 14, 2001 5:52 AM
Cc: [email protected]
Subject: [SI-LIST] : noise budgeting


I had a question about noise budgeting in SI design. As I understand,
the device noise margin varies for different devices, e.g., we have
noise margin of Voh (3.3V) - Vih(1.6 V) ~ 1.7 V for CMOS device. Out of
which, we have to budget for various type of noises, such as:

simutaneous switching noise;

Is there a guideline how much noise budget to be allocated to each type
of noise ? Also, there are different method to calculate the total
noise, e.g., direct sum up, which is a worse case design and root square
sum, which seems to be more realistic. Which method do you use in your
SI design ?

To complicate the issue, on a system level SI design, we may have to
allcoate noise budget for IC packagings, PCBs and other interconnects
(e.g., connectors). How is this done ?

Thanks in advance for your feedback.


Perry Qu

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