From: Perry Qu ([email protected])
Date: Wed Mar 14 2001 - 05:51:52 PST
I had a question about noise budgeting in SI design. As I understand,
the device noise margin varies for different devices, e.g., we have
noise margin of Voh (3.3V) - Vih(1.6 V) ~ 1.7 V for CMOS device. Out of
which, we have to budget for various type of noises, such as:
simutaneous switching noise;
Is there a guideline how much noise budget to be allocated to each type
of noise ? Also, there are different method to calculate the total
noise, e.g., direct sum up, which is a worse case design and root square
sum, which seems to be more realistic. Which method do you use in your
SI design ?
To complicate the issue, on a system level SI design, we may have to
allcoate noise budget for IC packagings, PCBs and other interconnects
(e.g., connectors). How is this done ?
Thanks in advance for your feedback.
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