**From:** Eric Bogatin (*eric@gigatest.com*)

**Date:** Tue Mar 13 2001 - 12:21:36 PST

**Next message:**Zabinski, Patrick J.: "RE: [SI-LIST] : differences in memory speeds"**Previous message:**John Lipsius: "RE: [SI-LIST] : differences in memory speeds"**Next in thread:**Brian Young: "Re: [SI-LIST] : approximations for partial self inductance"**Reply:**Brian Young: "Re: [SI-LIST] : approximations for partial self inductance"

Itzhak-

you asked the question about the difference in the approximations

for the partial self inductance of a via that were given by

myself and Howard Johnson. I wanted to provide some

clarification. You wrote:

(4) While calculating vias inductance, I've encountered 2 similar

but

different equations for this parameter. One is given by Mr. H.

Johnson

in his famous book (page 259), as follows:

L=5d*{ln(2d/r)+1}nH.

The other is given by Mr. Bogatin in one of his articles, and is:

L=5d*{ln(2d/r)-3/4}nH.

Can somwone explain the reason for the difference, or who is

right? The

difference starts to be quite critical when dealing with u-Vias!

The approximation is for the partial self inductance of a round,

solid rod, of radius, r and length d. The length is in units of

inches, while the inductance is in units of nH.

This is the approximation that was originally derived by Fred

Grover, in his classic book, Inductance Calculations", in 1946. I

just re-checked the one I offered, and it is correctly reproduced

above. It is listed on page 35, eq 7, of his book. I think it has

since been reprinted as a Dover Book.

Keep in mind two things when using this approximation: 1st, it is

an approximation. Grover says it is good to about 2%. I have

found good agreement to better than 5% for wire bond structures.

Approximations are wonderful tools to assist you in exploring

design space, run in a spread sheet and play what-if trade offs.

They give you good answers and let you see the geometry and

materials trade offs. However, they are APPROXIMATIONS. You

should never use an approximation in a situation where the

accuracy of the answer may cost you significant time and expense.

You should be using a 3D field solver that you have confidence

in. One of the second order effects in this approximation, for

example, is that it includes the "internal" self inductance. As

the skin depth gets to be comparable to the geometrical cross

section, the partial self inductance will decrease and reach a

constant value when all the current is in the outer surface.

The second thing to keep in mind when using this approximation is

that it is for the PARTIAL self inductance of the via, under the

assumptions of uniform current flow down the long axis. If you

are using it in a situation where the length of the structure is

comparable to the diameter, ie, d ~ 2r, the current distribution

through the structure may not be even close to parallel to the

long axis. Further, the actual loop inductance, which is what

matters in a real circuit, is probably dominated by other

elements than this small, squat element. The partial self

inductance may depend strongly on the proximity of other

conductors and how it affects the current flow through this via.

If you are in a regime where worrying about the presence of the

-3/4 term is important, you probably want to use a 3D field

solver before any design signoff. A good 3D solver will calculate

the actual current distribution through the via structure and the

rest of the current path.

I hope this helps.

If anyone is interested, I have various application notes related

to approximations to inductance and general principles related to

inductance posted on our web page. These are listed as app notes

with index numbers: 33, 32, 29, 25, and 9. You can find them

under application notes at www.gigatest.com

As always, comments are welcome.

--eric

From: Itzhak Hirshtal [mailto:hirshtal@is.elta.co.il]

Sent: Monday, March 12, 2001 09:33

To: si-list

Subject: [SI-LIST] : Inductance and Decoupling

Hello, all

I've recently started to calculate the de-coupling needed for

efficiently supplying the spike currents needed by high-speed

devices.

During this task, I've encountered several ambiguities and

results that

I would like to share with you and perhaps hear some (useful)

feedback

from you.

(1) I tried to evaluate the situation for one high-pin-count

device with

several buses connected to it (essentially a bus bridge). Even

calculating for just one synchronous bus (with 144 bits overall)

I

arrived to the result that a few Amps (maybe even 5) are drawn

when all

or most of this bus bits change state. I wonder what will be the

result

if I would calculate for an additional bus (assuming it's

synchronous

with the first). And what about the internal changes? They might

be

contributing even more than the external bus! (e.g., the Motorola

PowerPC HW manual states that 90% of the power consumption of

this

device is drawn internally, not externally).

(2) I've also tried to calculate the inductance of the decoupling

capacitors connections to the device. Even assuming a 40-mil wide

50-mil

long trace right above a reference plane for the connection I

have app.

L=150-200pH. If I can't connect at least one of the capacitor

pads so

short I might have to do a direct connection via to a reference

plane. I

calculated this to have more than L=1nH!

(3) I assumed the calculated peak currents change at a rate

equivalent

to the rise time of the device's output buffers. I don't know if

it's

true, but this seems to me the most logical thing to do. Even if

I take

it to be 2ns (1 ns is closer to worst-case, I believe), I get

the

result that I need 40 to 50 low-ESL decoupling capacitors for the

case

where L=1nH. Only if I succeed to connect the capacitors directly

and

close enough to both GND and VDD pins (L=150-200pH) do I get the

result

that it is sufficient to use 4-6 decoupling capacitors.

(4) While calculating vias inductance, I've encountered 2 similar

but

different equations for this parameter. One is given by Mr. H.

Johnson

in his famous book (page 259), as follows:

L=5d*{ln(2d/r)+1}nH.

The other is given by Mr. Bogatin in one of his articles, and is:

L=5d*{ln(2d/r)-3/4}nH.

Can somwone explain the reason for the difference, or who is

right? The

difference starts to be quite critical when dealing with u-Vias!

Thanks for anyone who makes the effort to read this email.

- --

Itzhak Hirshtal

Elta Electronics

POB 330 Ashdod

Israel 77102

Tel: 972-8-8572841

Fax: 972-8-8572978

email: hirshtal@is.elta.co.il

**************************************

Eric Bogatin

CTO, Giga Test Labs

v: 913-393-1305

f: 913-393-1306

e: eric@GigaTest.com

corporate office:

408-524-2700

134 S. Wolfe Rd Sunnyvale, CA 94086

web: www.gigatest.com <http://www.gigatest.com>

**************************************

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**Next message:**Zabinski, Patrick J.: "RE: [SI-LIST] : differences in memory speeds"**Previous message:**John Lipsius: "RE: [SI-LIST] : differences in memory speeds"**Next in thread:**Brian Young: "Re: [SI-LIST] : approximations for partial self inductance"**Reply:**Brian Young: "Re: [SI-LIST] : approximations for partial self inductance"

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