RE: [SI-LIST] : differences in memory speeds

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From: Michael Nudelman (mnudelman@tellium.com)
Date: Tue Mar 13 2001 - 05:47:06 PST


Pat,

I had few years ago a weird experience with SRAM, where it failed by
producing out-of-this-world values in the read cycles. It was SIMTEK SRAM
with backup option. After consultation with SIMTEK I decided to look at WE-
signal, and found a long negative overshoot. According to SIMTEK, the device
could go into "weak write" mode because of WE- being lower than GND (and,
respectively, than other signals). After I series-terminated teh WE-, the
problem stopped.

It is possible that faster device is more succeptible to small transitions.
Also, I had a inexpicable problem once with TOSHIBA 82C54 counters, wher
EVERY manufacturer except TOSHIBA worked fine; TOSHIBA would reset itself
(count as well as mode of operation) for no obvious reason. The problem
manifested itself ONLY when BurrBrown DCDC converter was used for supplying
5V, while others DCDCs would make the board work fine.

My investigation found the device was more sensitive to noise from DCDC
converters; I had to REALLY de-couple the input and output of the DCDC to
make it work; but eventually I just restricted my BOM to all mfr. minus
Toshiba.

Mike.

-----Original Message-----
From: Zabinski, Patrick J. [mailto:zabinski.patrick@mayo.edu]
Sent: Monday, March 12, 2001 10:00
To: si-list@silab.eng.sun.com
Cc: Zabinski, Patrick J.
Subject: [SI-LIST] : differences in memory speeds

To all:

We designed a system around asynchronous SRAM memories with 20 nsec
access times. When we put the system together, it worked
great.

For several reasons, we ran short of the 20 nsec parts, and we
were forced to populate subsequent boards with 17 nsec parts.
The two parts are stated to be "identical" with the
exception of the different access times (i.e., they share
a common data sheet, part number, mfr, package, etc.; they
simply have different speed ratings).

When we populate our system with the 17 nsec parts, the
system fails, and we are trying to understand the differences
between the two different speed parts. Any clues?

For background, the memories are part of a daisy chain
net that is driven by a source-series terminated source.
The driver's output impedance roughly matches that of the
line, so the initial signal out of the driver rides at
about VDD/2 until the reflected wave makes its way back.
The memory parts at the far end of the line work fine,
while the parts at the near (driver) end of the line
are the ones having difficulty. Our suspicion is that the
initial pulse is too close to threshold for the 17 nsec
parts, which is causing the problems. However, the
17 and 20 nsec parts are spec'd to have the same
thresholds.

Even if the two parts did have different thresholds, because
they are asynch SRAMS (i.e., supposedly not edge-triggered???),
riding at/near threshold should not theoretically be
a problem.

Anyone out there tell me where I'm off in my thinking,
experience something similar, or have some insight to
the differences between the 17 and 20 nsec parts (other
than access time)? I tried to simulate the difference,
but the two parts use the same spice models.

Thanks,
Pat

P.S. Are different speed memories designed/fab'd differently,
or are they simply 'binned' depending upon effective
resulting wafer lot process parameters?

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