Re: [SI-LIST] : Simulation of address and data bus

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From: KokTongTHAM (kt_tham@uti2000.co.jp)
Date: Sun Mar 11 2001 - 23:11:50 PST


SI Gurus.

Thanks for your information.

Regards,
KT.THAM

At 08:46 01/03/08 -0500, you wrote:
>KT,
>
>The only one I know of that will generate pseudo-random patterns is
>SPECCTRAQuest from Cadence. Other SPICE-based tools and XTK will let
>you set up patterns manually. The last time I looked at Hyperlynx I
>saw no pattern feature, but I wasn't looking for that. I am not sure
>at all what ICX has. Admittedly you need one of the more expensive
>tools to have this feature.
>
>Mike
>
>KokTongTHAM wrote:
> >
> > Dear Mike LaBonte,
> >
> > Can you let me know which SI tools can apply random data patterns?
> >
> > Thanks.
> >
> > Regards,
> > KT.THAM
> >
> > At 午前 12:42 01/03/08 -0500, you wrote:
> > >Bhavesh,
> > >
> > >I would recommend running logic patterns for data and address, even if
> > >you do it for only one signal at a time. As long as there is enough
> > >charge storage on the net to make a measurable difference one edge later,
> > >the possibility of pattern dependent ISI should be investigated. I
> > >don't think you can run your data at any regular frequency and rest
> > >assured that all bases are covered.
> > >
> > >There are SI tools that will apply random patterns or patterns that you
> > >determine.
> > >
> > >Mike LaBonte
> > >
> > >"Patel, Bhavesh" wrote:
> > > >
> > > > Hi! I had a question regarding simulations of address and data bus at
> > > > particular frequencies. Say, if the chip is being clocked at 166Mhz do
> > > we do
> > > > simulations of the address and data bus to the chip at 166Mhz or do we
> > > do it
> > > > at half the clock frequency.? What would give an approx real world
> > > scenario,
> > > > simulation at the clock frequency or half the clock frequency?
> > > >
> > > > Thanks
> > > > Bhavesh
> > > >
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