RE: [SI-LIST] : 400MHz Source Synchronous Existance Proof?

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From: Ronald E. Nikel (renikel@tricn.com)
Date: Fri Mar 09 2001 - 05:57:17 PST


Brad,

Asked this question 10 years ago the answer would have been no. To my
knowledge SCI was one of the first commercially standardized and available
that addressed this issue. Every machine shipped from SGI since 1994 has
had something known as Craylink which was a 400Mb/s DDR elastic buffer
interface integrated into nearly every ASIC. Standards today that are close
to what you describe would be AGP4X which is 266Mb/s which has to be one of
the more reliable standards in high volume production.

There are several proprietary standards from various companies that are all
operating in the 500Mb/s to 3.125Gb/s DDR either in production today or
about to put to production. And for those of you who don't grimace you can
always point to RamBus as being an example of a fairly high volume DDR
interface standard that operates up to 800Mb/s.

So in short I think the field is crowded with interfaces that operate in the
mid 100's MHz. Careful specmanship and attention to detail will make it
extremely easy to produce.

Ron.

-----Original Message-----
From: owner-si-list@silab.eng.sun.com
[mailto:owner-si-list@silab.eng.sun.com]On Behalf Of Bradley S Henson
Sent: Thursday, March 08, 2001 10:47 AM
To: si-list@silab.eng.sun.com
Subject: [SI-LIST] : 400MHz Source Synchronous Existance Proof?

For years I've been following IEEE 1596.3, SCI, various LVDS offerings, DDR
SRAMS etc. It would appear that given good engineering, we can send
parallel data with a clock over short distances ( a couple of inches) in a
point_to_point topology. RAMBUS seems to have faultered in the PC
environment mainly because of the multi_drop nature of the 3 memory cards,
although I'm sure there are many other opinions. I've personally done
source synch. to about 200MHz and serial to over 1GHz without great
problem. My question for the group is: Are 400MHz source synchronous
designs fairly common today or are they generally considered high-risk? Are
there any existance proofs fielded I can cite? In my case we will have
very fast (not CMOS) ASICs doing the sending and receiving, so elastic
buffers and appropriate attention to detail will be within our control. The
interface will be a low voltage swing differential, maybe PECL or CML.

Thanks,
Brad Henson, Raytheon

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