Re: [SI-LIST] : Simulation of address and data bus

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From: Jim Freeman (freeman@broadcom.com)
Date: Thu Mar 08 2001 - 10:31:17 PST


I do this using Hspice

Jim Freeman

Mike LaBonte wrote:

> Bhavesh,
>
> I would recommend running logic patterns for data and address, even if
> you do it for only one signal at a time. As long as there is enough
> charge storage on the net to make a measurable difference one edge later,
> the possibility of pattern dependent ISI should be investigated. I
> don't think you can run your data at any regular frequency and rest
> assured that all bases are covered.
>
> There are SI tools that will apply random patterns or patterns that you
> determine.
>
> Mike LaBonte
>
> "Patel, Bhavesh" wrote:
> >
> > Hi! I had a question regarding simulations of address and data bus at
> > particular frequencies. Say, if the chip is being clocked at 166Mhz do we do
> > simulations of the address and data bus to the chip at 166Mhz or do we do it
> > at half the clock frequency.? What would give an approx real world scenario,
> > simulation at the clock frequency or half the clock frequency?
> >
> > Thanks
> > Bhavesh
> >
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