RE: [SI-LIST] : Why all reset signals are active low?

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From: Thomas Jackson (tjackson@fmi.fujitsu.com)
Date: Mon Mar 05 2001 - 09:13:07 PST


In addition to the following explanation, in the old bipolar TTL days, there
was significant current flow. Since the source current for a LOGIC "1" was
much lower than the sink current of a LOGIC "0", having the deasserted
state, where a reset signal spends most of the time, as a LOGIC "1" consumed
less power than the opposite.
 
Tom
Thomas L. Jackson, P.E.
Staff VLSI Design Engineer
Network Access Development
Systems Solutions Group
FUJITSU MICROELECTRONICS, INC.
3545 North First Street
San Jose, CA 95134-1804
telephone: (408) 922-9574
facsimile: (408) 922-9618
http://www.fujitsumicro.com

-----Original Message-----
From: Ashok Prabhu Masilamani [mailto:ashok.prabhu@wipro.com]
Sent: Monday, March 05, 2001 1:24 AM
To: selvaraj subramanian ; si-list@silab.eng.sun.com
Subject: Re: [SI-LIST] : Why all reset signals are active low?

Hello,
 
      Mostly all critical signals like reset, CS etc are active low because
of the input noise tolerance of the logic levels of the logic families.
take the case of TTL where the V(ih) = 2V and V(il) = 0.8V. It means a
voltage upto 0.8V can be detected as logic low by the device and a voltage
as low as 2V can be detected as logic one. so, for a logic low input a noise
voltage of 2V can make the device to detect it as logic one which is not the
case for logic one. so logic one has more noise tolerance. This is the case
for most of the logic families.
 
      this is the reason reset signals are active low. In deasserted state
they will be in logic level one which means it won't switch to the logic
level zero even if a noise input of greater magnitude affects it. otherwise
if it had been a active high system, the system would get reset even for a
noise input of small magnitude.
 
      Even though i have not put forward my explanation in a proper flow, i
think i have answered your question.
 
ashok

----- Original Message -----
From: selvaraj subramanian <mailto:selvaraj.manian@wipro.com>
To: si-list@silab.eng.sun.com <mailto:si-list@silab.eng.sun.com>
Sent: Monday, March 05, 2001 9:37 AM
Subject: [SI-LIST] : Why all reset signals are active low?

Hello,
 
Why all reset signals are active low?
 
Can anyone suggest me on this regard.
 
Which one will be preferrable (active low reset or active high reset) and
why?
 
thanks in advance.
 
regards,
Selva
 
 
 
 
 
 
 
 
 



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