Re: FW: [SI-LIST] : Bypass Cap via placement considered. Negative L's?

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From: RMELLISON@aol.com
Date: Mon Mar 05 2001 - 03:36:39 PST


Hi all.
I think I got in on the tail end of this discussion, but I need some
clarification.
I've built hf circuit cards in the past where I've used multiple vias to
ground from each bypass capacitor. The intent was to reduce the inductance
of the path to the ground plane. Was I possibly making the inductance
higher because of mutual inductance effects? If so, what's a good rule of
thumb for via separation in order to avoid this problem?
Rich Ellison

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