# RE: [SI-LIST] : Clock routing width/impedance

From: Steve Rogers ([email protected])
Date: Thu Mar 01 2001 - 00:04:56 PST

Some points...

1. Crosstalk is a function of

(a) The separation of the traces
(b) The source and load impedances of the traces
(c) The signal frequency on the trace

Keeping things very basic. If the impedances are low then the trace carries
large currents. The circuit is then predominantly a radiator or is more
susceptible to inductive effects. If the impedances are high the situation
is the opposite. In this case capacitive effects are the problem (What are

Point b is easy to prove with a simple analsis of two circuits, both with a
source and a load. Put a capacitor between the two and analyse for cap
effects, do the same with inductors in each circuit coupled by 'k' for
inductive effects. You will then see the relationship between crosstalk and
the source and load impedances, which incidently suggests opposite values
for source/load impedance for minimum crosstalk dependant on whether the
effect is cap or inductive (you need to determine which one it is!!!!!)

Next. I think the width of the trace will be a factor in crosstalk. If you
think about it if the trace is very very wide then the fringing fields will
be small (both E and H) in this case the ground plane soaks up most of your
field. However you need more real estate and for fixed position of victim
trace and centre of source trace your effectively getting nearer (oops).

Your trace width may already be defined? In many cases you will need to have
a set trace Zo in order to match the line to the source/load to minimise
reflections. In this case the trace width for a fixed layer assignment is
fixed anyway. Incidently if your going multilayer and you want more for your
money go for coplanar guide (sandwiched trace between upper/lower returns.
.
Without more info (how much isolation, layout constraints etc) this is about
all I can say

Hope this helps

SGR

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