From: Mike Saunders ([email protected])
Date: Wed Jun 06 2001 - 09:25:11 PDT
Binoj,
Since you are interfacing two different signaling levels, place the DC bias
resistors and AC coupling caps as close to the fo transceiver input as
possible. Place the thev. termination for the PECL driver immediately
before the AC caps (the ECL outputs need a DC path to VEE, so the
termination must occur BEFORE the AC coupling). You are correct to set the
DC bias to 1.96V for your inputs, but the thev. termination for the PECL
load should be terminated to 1.3V through the equivalent of 50ohms (you
could also use a "Y" or "middle stub" termination on your PECL diff. pair).
The AC coupling caps in the middle will take up the slack, but you'll get
some RC delay and edge rate degradation using them. Make sure you simulate
at speed for your application.
Another alternative for level-shifting would be to use a resistor tree.
Both level-shifting and termination techniques for PECL are detailed in
some good app notes by On-Semi, which can be found at:
http://www.onsemi.com/pub/Collateral/AN1568-D.PDF
or
http://www.onsemi.com/pub/Collateral/AND8020-D.PDF
--Mike
HELLO ALL,
I am using a differential pecl to ttl and ttl to differential
pecl translator in my design in which the differential pecl o/p is using to
drive one fo transceivers(hfbr 5903).As the fo transceiver i/p are in a
different level I used capacitor coupling and biased the differential o\p
at the fo i/p side.what I did is, biased the lines to middle of fo i/p
(1.96v) with a thevenin termination which provides a 50 ohm impedance.
But what I read is that the termination voltage should be vcc-2,i.e.
1.3v(3.3-2).How can I satisfy both of this condition or I am doing
something false?The fo I/p levels are as follows
vil min-1.49v vil max-1.825 vih min-2.135 vihmax-2.42
Thanks for replying
Binoj
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