[SI-LIST] : Diff clock topology and timing

From: dkhatri ([email protected])
Date: Fri Jun 01 2001 - 08:11:57 PDT

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Hi Everyone,
I am trying to come up with the best diff. clock topology for the
unbuffered DDR modules. Trying with different topology I get the better
signal integrity with the topology I like to have but the min/max flight
time is slower by ~200 ps than the rest of the other topology. I am trying
to get a feeling how much will this hurt us in the set up and hold time. Any
thoughts

Appreciate your inputs.

Thanks,
Dirgha Khatri
Simulation Engineer
Micron Technology

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