From: Goutham Sai ([email protected])
Date: Fri May 18 2001 - 00:42:07 PDT
Hello Everybody !
why most high speed PCB's clock signals are routed with more than 10mil width Cu traces. why separate layers for clock signals is required.
For a PC mother board design with PII processor, GTLP signals & differential signals please suggest best 10 layer pcb stackup.
i have designed the following layer stackup for the above config. Please comment on the following layer stack-up.
--------------top
--------------gnd1
--------------clock1 with Cu islands&shieldings
--------------GTLP signals & HS signals
--------------vcc
--------------GTLP signals
--------------V3_3
--------------clock2 with Cu islands&shieldings
--------------gnd2
--------------Bottom
your advice greatly appreciated.
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This archive was generated by hypermail 2b29 : Thu Jun 21 2001 - 10:12:00 PDT