From: S. Weir ([email protected])
Date: Wed May 09 2001 - 13:16:31 PDT
Bhavesh,
I think that you may be confused by noise on the ground.
Think SPICE node0 at PLL "GND" inside the chip. You want the PLL Vcc to
track the local ground at the PLL circuitry inside the chip across the
spectrum. So you ideally want zero impedance between PLL Vcc and that
potential, and no external current flow. In reality, we can't get zero
impedance, so we are limited to controlling the external current flow.
Since our node is at the same AC potential as ground, without a filter,
digital signals will use the PLL Vcc as just another AC return.and impress
noise voltages on the PLL Vcc. The filter is to block these return
currents. We need to make sure that the filter is not defeated by the
layout. My recommendation is in the attached GIF file.
For this approach, anchor the PLL Vcc to ground at the nearest ground ball
as the Vcc pin, and keep both the PLL Vcc, and return ground as seen by the
filter as close to that AC GND as possible by enclosing them between GND
planes as they route to the passive filter components.
In the area of the passive filter components, put keep-outs on layers above
the enclosing upper GND. The further down the uppermost GND is, the wider
the void periphery. Make sure you keep these parts away from magnetics and
/ or optics.
You can extend the concept in the picture to a polygon fill on the PLL Vcc
and GND tracks to reduce the series impedance between the decoupling cap C,
and the PLL Vcc pin. But this really should not be necessary.
Good luck.
Regards,
Steve.
At 11:37 AM 5/9/01 -0700, you wrote:
>Hi! In my case the PLL power pins are somewhere in the middle for a BGA and
>I cannot get a 20mil trace to the pin so using a plane but where I am
>getting confused is that by using isolated plane approach I can take care of
>the noise rejection but the filter components are connected to gnd so
>wouldn't I pick up noise from there(gnd). I am not advocating cutting up the
>gnd plane but I am trying to justify using this isolated plane approach for
>a single PLL power pin.
>Thanks for all the inputs so far, its a real help
>Bhavesh
>
>
>-----Original Message-----
>From: Michael Nudelman [mailto:[email protected]]
>Sent: Wednesday, May 09, 2001 5:09 AM
>To: Patel, Bhavesh; SI_LIST (E-mail)
>Subject: RE: [SI-LIST] : Power filtering?
>
>
>Bhavesh:
>
>What we did (successfully) - we did not cut out planes; for PLL power we
>just used two-pole LC filter (actually Ferrite-C and LC filter), and fat
>trace around the chip. Right now we will do the experiment on the RC filter.
>
>
>Mike.
>
>-----Original Message-----
>From: Patel, Bhavesh [mailto:[email protected]]
>Sent: Tuesday, May 08, 2001 9:24 PM
>To: SI_LIST (E-mail)
>Subject: [SI-LIST] : Power filtering?
>
>
>Hi! Gurus, I had a question regarding the amount of noise rejection that can
>be achieved 1)by using a filter 2) using separate power plane.
>If the IC manufacturer said that the PLL power to be supplied has to be
>'clean' then he is mentioning about the noise rejection that he would like
>to have on these power pins that feed power to his internal PLL's.
>The manufacturer will typically recommend an RC filter and I believe the IC
>mfgr has verified on his test board that this the filter values that will
>achieve the noise rejection.
>Now, some designers want to cut up the power plane i.e. say from the main
>3.3V plane cut up a small portion use the Resistor as a bridge to feed the
>power to the island.
>I believe we have achieved two levels of rejection 1)filter 2) cut up plane.
>
>Can I just use the filter and not cut up the power plane and if I have to
>how do I calculate the noise rejection number by using the filter & using
>the island approach.
>Thanks in advance
>Bhavesh Patel
>
>
>
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