From: [email protected]
Date: Wed Apr 18 2001 - 10:02:10 PDT
>To all the experts, I would like to get some feedback on a couple of
issues:
> Board dimension is about 4"X8"
> signal1
> gnd2
> signal3
> signal4
> power5
> signal6
> signal7
> power8
> signal9
> signal10
> gnd11
> signal12
Hi E,
I'm a layout person, and would suggest a couple of things.
1) add the buried capacitance layers (GND plane) to power5&8. This will
allow you no impedance discontinuities to a couple of your signal
layers, and give you additional return path "paths". Buried capacitance
layering is only additional copper layers and ~.002" dielectric material
(doesn't add much to your stackup), and doesn't remove any of your six
routing layers. Most all "good" fab shops can handle this requirement,
if not, find one.
2) Route as much of the signals going across any remaining splits around
the splits, as much as possible. Again, it's to you to determine what is
critical. I've sat with an engineer that wouldn't allow me to cross the
splits, and as we sat he contemplated which signals were crossing
(critial vs. non-critical) and found he really didn't care about certain
signals. Some were just not important to him. I don't recommend going
across splits 50-100mils, because that causes large reflections and
what-not, but I've crossed 10-20mil splits, no problem. As long as your
non-critical signals route predominately over "a" reference plane you
achieve acceptable impedance.
Hope this helps.
Mitch
_____________________________________________________________
Tired of limited space on Yahoo and Hotmail?
Free 100 Meg email account available at http://www.dacafe.com
**** To unsubscribe from si-list or si-list-digest: send e-mail to
[email protected]. In the BODY of message put: UNSUBSCRIBE
si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu
****
This archive was generated by hypermail 2b29 : Thu Jun 21 2001 - 10:11:38 PDT