From: [email protected]
Date: Mon Mar 05 2001 - 09:30:57 PST
Another reason why reset signals are low is for power on reset issues. When
the
power supply rises most systems require rests to be asserted. If the reset
is
active low a simple RC power on reset circuit can be connected to the pin.
This
will normally assure that the reset can be active during the power supply
ramp.
If the reset was active high a more complicated circuit would have to be
used. As an IC designer, chip resets are nornally low, unless the
reset state is to be avoided.
As far as internal chip signals, this is often left up to the individual
designer. The question is always which state should normal
operation be permitted: logic low or high?
Best Regards,
Bill Cohen
Eastern Region Circuit Design
Toshiba America Electronic Components
"Ashok Prabhu Masilamani" <[email protected]>@silab.eng.sun.com on
03/05/2001 04:24:23 AM
TOSHIBA
Please respond to "Ashok Prabhu Masilamani" <[email protected]>
Sent by: [email protected]
To: "selvaraj subramanian " <[email protected]>,
<[email protected]>
cc:
Subject: Re: [SI-LIST] : Why all reset signals are active low?
Hello,
Mostly all critical signals like reset, CS etc are active low because
of the input noise tolerance of the logic levels of the logic families.
take the case of TTL where the V(ih) = 2V and V(il) = 0.8V. It means a
voltage upto 0.8V can be detected as logic low by the device and a voltage
as low as 2V can be detected as logic one. so, for a logic low input a
noise voltage of 2V can make the device to detect it as logic one which is
not the case for logic one. so logic one has more noise tolerance. This is
the case for most of the logic families.
this is the reason reset signals are active low. In deasserted state
they will be in logic level one which means it won't switch to the logic
level zero even if a noise input of greater magnitude affects it. otherwise
if it had been a active high system, the system would get reset even for a
noise input of small magnitude.
Even though i have not put forward my explanation in a proper flow, i
think i have answered your question.
ashok
----- Original Message -----
From: selvaraj subramanian
To: [email protected]
Sent: Monday, March 05, 2001 9:37 AM
Subject: [SI-LIST] : Why all reset signals are active low?
Hello,
Why all reset signals are active low?
Can anyone suggest me on this regard.
Which one will be preferrable (active low reset or active high reset) and
why?
thanks in advance.
regards,
Selva
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