I've put together this web page so that the schematics, sketches, and bits and pieces of descriptive text I've done on this project will be easily accessible to anyone kind enough to offer their comments and suggestions.

Last update: July 25/02

Still adding initial text & links. More to come when I get a chance.

At the time this page is being created, development is underway on a preliminary board which implements the passband analysis function as an independent module with an interface suitable for testing various grid-dip implementations. The module uses a parallel port (i.e. bit bang) control strategy rather than the USB interface planned for future versions in order to defer much of the software development work. An initial grid-dip probe design (a series resonant variation) is also included as part of this initial effort.

Overview:

The Grid-dip Gizmo grew out of a need for a piece of equipment to help me tweak a bunch of very narrow band, small loop antenna modules to their correct resonant frequency. What I wanted was something where after each little adjustment I could simply set the module on top, press a button, and read the new resonant frequency off a display. The idea was to detecting the sharp increase in the amount of energy "absorbed" by the module as an RF field from a variable frequency oscillator (VFO) was swept past it's point of resonance. This has been the basic idea behind grid-dip meter designs for many years.

There were two aspects of the "classical" grid-dip design however that I did not want to include in my implementation. The first was coupling the device under test directly to the main inductor of the meter's L/C type VFO. I was looking for accuracy and stability levels that exceeded the capabilities of an L/C design so this approach had to go. The classic approach also operates the VFO with the bare minimum of positive feedback - often using a variable attenuator in the feedback path to ensure this. The idea is that as the amount of energy being coupled into the device under test rises, the VFO signal level drops by an even greater factor because there is no longer sufficient positive feedback for proper operation. As handy as "amplifying" the dip in this manner is, it doesn't make a lot of sense when your oscillator is a crystal controlled, PLL frequency synthesizer chip.

The changes above imply a major deviation from a classical grid-dip design. The classical approach uses the VFO's main inductor to both generate the RF coupling field and simultaneously sense the amount of energy being coupled into the device under test. With no L/C oscillator, the Grid-dip gizmo requires a pair of inductors and separates the two functions. More importantly the grid dip gizmo doesn't utilize "reflection" back from the device under test through the coupling field (i.e. to change the effective Q of a main inductor). Instead it uses a strategy of comparing the "receive signal strength" of the coupling field at it's "receiver" inductor with the calibration level established before the device under test is brought in.

It is important to realize that this design uses a two step testing process. An initial calibration sweep with no device under test must be performed at least once to establish the gain levels necessary at each discrete frequency point so that a perfectly flat "receive strength" reading is produced across the sweep. Subsequent sweeps then involve re-playing [frequency,gain-level] pairs and reporting the deviation in the receive strength reading from the calibration level.

More to follow soon. I'll integrate the items below into the page and set up an image map for the schematic (to D/L datasheets for each part) when I get a chance.

This is missing a few coupling caps and bias resistors but it's the basic Version 1 schematic . I've been adding additional bits (from the data sheets and app notes) as I do the layout - see below. The opto-isolated parallel port interface has now changed to a fully bi-directional version which I've decided to separate out as an independent module.

The initial probe design is the one with the rounded loops, the other three just show possible testing orientations.

The layout artwork has stalled at this point as I fool around with bi-directional opto-isolator designs. As far as the main board is concerned the interface has been reduced to a 4 pin connector (i.e. +5/gnd/SCL/SDA) once I get back to it. The conversion to a web-friendly gif has mucked up the image a bit but hopefully it's good enough to generate some comments regarding the use of a single side board or the way I've set up the break in the ground plane between the transmit and receive supply sections. Note that there are no holes/vias at this point. Other than the one main jumper across the bottle-neck between the two ground islands, the only jumpers are the SCL and SDA connections from each of the I2C devices to what will ultimately be a bunch of connection pads for the two busses coming out of the MAX4562 bus switch (eventually in the upper island above the receive side 78L05).

I'm a bit off track at the moment as I try to implement a "true" parallel port to I2C interface. None of the public domain software packages I've found support a bi-directional SCL line (with the corresponding monitoring during periods of SDA inactivity, etc). Without this ability there is no way for I2C slaves to implement a "not ready" state (i.e. by holding SCL low after the master releases it) or for an external bus master to negotiate with the PC for control of the bus (as described in the I2C spec). At the moment I'm bogged down in XP specific considerations regarding parallel port access. I'm trying to get a couple of JNI compliant support functions (in C) working so I can write everything else for the Java runtime environment. Where I'm having trouble is linking up with the enhanced parallel port's interrupt support capability (so I don't have to poll SCL continuously to support a PC slave configuration).

PLEASE - email me your comments, suggestions, musings, rants, or anything else

Thanks,
Mike (va4mgw)