Memory control logic for 68020 system.


#	date		description					by
--	--------	------------------------------------------	----
01	20/02/95	initial version					BDJ
02	25/02/95	added 16 bits bus using /lds & /uds		BDJ
03	15/08/95	included cpu-workspace (fpu & mmu -> berr)	BDJ

In the following scheme is showed how ram0-3 are decode as a logical
comination of siz1/siz0 and a1/a0.
Note that not all combinations are legal, but you never know...

siz1	siz0	# of bytes to write
-----------------------------------
0	0		4
0	1		1
1	0		2
1	1		3

siz1	siz0	a1	a0	we0	we1	we2	we3	uds	lds
-----------------------------	--------------------------------------------
0	0	0	0	1	1	1	1	1	1
0	0	0	1		1	1	1		1
0	0	1	0			1	1	1	1
0	0	1	1				1		1
-----------------------------	--------------------------------------------
0	1	0	0	1				1
0	1	0	1		1				1
0	1	1	0			1		1
0	1	1	1				1		1
-----------------------------	--------------------------------------------
1	0	0	0	1	1			1	1
1	0	0	1		1	1			1
1	0	1	0			1	1	1	1
1	0	1	1				1		1
-----------------------------	--------------------------------------------
1	1	0	0	1	1	1		1	1
1	1	0	1		1	1	1		1
1	1	1	0			1	1	1	1
1	1	1	1				1		1

(c) PE1JPD

CHIP  memcntr 20v8

; pin  1     2     3     4     5     6     7     8     9     10    11    12
       nc    siz1  siz0  a1    a0    fc0   fc1   a19   a18   a17   a16   GND

; pin  13    14    15    16    17    18    19    20    21    22    23    24
       nc    berri /we0  /we1  /we2  /we3  /berr /lds  /uds  /avec /wr   VCC

@ues memcntr

EQUATIONS

we0	=	 wr*/a1*/a0

we1	=	 wr*/a1          * siz1 +
		 wr*/a1* a0             +
		 wr*/a1          */siz0

we2	=	 wr* a1*/a0             +
		 wr*/a1    */siz1*/siz0 +
		 wr*/a1    * siz1* siz0 +
		 wr*/a1* a0* siz1

we3	=	 wr        */siz1*/siz0 +
		 wr* a1    * siz1       +
		 wr* a1* a0             +
		 wr* a1          */siz0 +
		 wr    * a0* siz1* siz0

avec	=	 fc0 * fc1 *  a19 *  a17

uds	=	/a0

lds	=	 siz1 + /siz0 +  a0

berr	=	 fc0 * fc1 * /a19 * /a17
	+	 fc0 * fc1 * /a19 *  a17
	+	 berri